From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH 3/8] x86/AMD: Read VPMU MSRs from context when it is not loaded into HW Date: Wed, 19 Jun 2013 19:53:51 -0400 Message-ID: <51C2448F.6060701@oracle.com> References: <1365528379-2516-1-git-send-email-boris.ostrovsky@oracle.com> <1365528379-2516-4-git-send-email-boris.ostrovsky@oracle.com> <5167004B.2000905@amd.com> <51670247.1090409@oracle.com> <20130416154151.GD2799@phenom.dumpdata.com> <20130416171216.GA18385@jshin-Toonie> <20130416183644.GE9417@phenom.dumpdata.com> <51C23713.6020301@amd.com> <51C23F96.5080509@oracle.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============6523118862272670031==" Return-path: In-Reply-To: <51C23F96.5080509@oracle.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Suravee Suthikulanit Cc: Konrad Rzeszutek Wilk , George Dunlap , "haitao.shan@intel.com" , "Shin, Jacob" , "dietmar.hahn@ts.fujitsu.com" , "xen-devel@lists.xen.org" , "jun.nakajima@intel.com" List-Id: xen-devel@lists.xenproject.org This is a multi-part message in MIME format. --===============6523118862272670031== Content-Type: multipart/alternative; boundary="------------010704080901030501080108" This is a multi-part message in MIME format. --------------010704080901030501080108 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On 06/19/2013 07:32 PM, Boris Ostrovsky wrote: > On 06/19/2013 06:56 PM, Suravee Suthikulanit wrote: >>> > >>> > http://lists.xen.org/archives/html/xen-devel/2013-04/msg01028.html: >>> > >>> > diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c >>> > index 17efc0f..c269468 100644 >>> > --- a/tools/libxc/xc_cpuid_x86.c >>> > +++ b/tools/libxc/xc_cpuid_x86.c >>> > @@ -112,6 +112,7 @@ static void amd_xc_cpuid_policy( >>> > bitmaskof(X86_FEATURE_XOP) | >>> > bitmaskof(X86_FEATURE_FMA4) | >>> > bitmaskof(X86_FEATURE_TBM) | >>> > + bitmaskof(X86_FEATURE_PERFCTR_CORE) | >>> > bitmaskof(X86_FEATURE_LWP)); >>> > regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */ >>> > (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) | >>> > >>> > Or maybe not since vpmu is not on by default .. ? >>> >>> I would say not yet. As the vpmu=1 (at least on Intel) has some issues. >>> Until that is fixed and vpmu=1 is by default lets leave it as so. >>> >>> > >>> >> Konrad, Boris: >> I would like to ask you to reconsider accepting this patch for 4.3. > > I think it missed 4.3 anyway. OK, I think I misunderstood your question --- I thought you were asking to back out this patch because you found that something is broken with it. Instead you do want to have it in 4.3. Sorry. This is probably request for George then (but I suspect it's too late now). -boris > >> This bit and vpmu=1 are independent of each other. Without vpmu=1 option, PERF in HVM guest >> will not work regardless of this bit. So, it should be safe to always setting this bit. >> However, if user set vpmu=1 and not _manually_ setting this bit, the PERF logic will >> break and users will be getting incorrect result. > > > Why would you need to set this bit by hand in addition to having the > patch? With this patch I see ecx=0x00a18bf3. I.e. bit 23 is set, as > expected. > > -boris > > >> The bit is currently used in the Linux PERF logic for all family15h to >> tell that there are 6 counters instead of 4 counters (when bit the is not set). >> Also, it will be using a different set of event constrain. The current Linux PERF >> core PMU logic assume that this bit will always be available. --------------010704080901030501080108 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit
On 06/19/2013 07:32 PM, Boris Ostrovsky wrote:
On 06/19/2013 06:56 PM, Suravee Suthikulanit wrote:
>
> http://lists.xen.org/archives/html/xen-devel/2013-04/msg01028.html:
>
> diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
> index 17efc0f..c269468 100644
> --- a/tools/libxc/xc_cpuid_x86.c
> +++ b/tools/libxc/xc_cpuid_x86.c
> @@ -112,6 +112,7 @@ static void amd_xc_cpuid_policy(
>                       bitmaskof(X86_FEATURE_XOP) |
>                       bitmaskof(X86_FEATURE_FMA4) |
>                       bitmaskof(X86_FEATURE_TBM) |
> +                    bitmaskof(X86_FEATURE_PERFCTR_CORE) |
>                       bitmaskof(X86_FEATURE_LWP));
> regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
>                       (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
>
> Or maybe not since vpmu is not on by default .. ?

I would say not yet. As the vpmu=1 (at least on Intel) has some issues.
Until that is fixed and vpmu=1 is by default lets leave it as so.

> 

Konrad, Boris:
I would like to ask you to reconsider accepting this patch for 4.3.

I think it missed 4.3 anyway.


OK, I think I misunderstood your question --- I thought you were asking to back out this patch because you found that something is broken with it. Instead you do want to have it in 4.3. Sorry.

This is probably request for George then (but I suspect it's too late now).

-boris



This bit and vpmu=1 are independent of each other.  Without vpmu=1 option, PERF in HVM guest
will not work regardless of this bit. So, it should be safe to always setting this bit.
However, if user set vpmu=1 and not _manually_ setting this bit, the PERF logic will 
break and users will be getting incorrect result.


Why would you need to set this bit by hand in addition to having the patch? With this patch I see ecx=0x00a18bf3. I.e. bit 23 is set, as expected.

-boris


The bit is currently used in the Linux PERF logic for all family15h to
tell that there are 6 counters instead of 4 counters (when bit the is not set).
Also, it will be using a different set of event constrain. The current Linux PERF 
core PMU logic assume that this bit will always be available.

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