From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH 04/17] xen: arm: support building a 64-bit dom0 domain Date: Mon, 29 Jul 2013 19:29:32 +0100 Message-ID: <51F6B48C.8060503@linaro.org> References: <1375100431.14896.95.camel@kazak.uk.xensource.com> <1375100466-7564-4-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1375100466-7564-4-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 07/29/2013 01:20 PM, Ian Campbell wrote: > Signed-off-by: Ian Campbell > Acked-by: Stefano Stabellini My apologies, I didn't give a try of this patch series until now. This patch breaks DOM0 boot on the Arndale Board. > --- > v3: rebased. as part of this move PSR_GUEST_INIT out of the public interface > --- > xen/arch/arm/domain_build.c | 10 +++++++--- > xen/include/asm-arm/processor.h | 2 ++ > xen/include/public/arch-arm.h | 2 -- > 3 files changed, 9 insertions(+), 5 deletions(-) > > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index 155b436..dd54014 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -588,9 +588,7 @@ int construct_dom0(struct domain *d) > > memset(regs, 0, sizeof(*regs)); > > - regs->pc = (uint32_t)kinfo.entry; > - > - regs->cpsr = PSR_GUEST_INIT; > + regs->pc = (register_t)kinfo.entry; > > #ifdef CONFIG_ARM_64 > d->arch.type = kinfo.type; > @@ -598,6 +596,11 @@ int construct_dom0(struct domain *d) > > if ( is_pv32_domain(d) ) > { > + regs->cpsr = PSR_GUEST_INIT|PSR_MODE_SVC; > + > + /* Pretend to be a Cortex A15 */ > + d->arch.vpidr = 0x410fc0f0; It's not related to the bug. But why do you fake the VPIDR for each 32-bits guest even on real 32-bits hardware? > + > /* FROM LINUX head.S > * > * Kernel startup entry point. > @@ -615,6 +618,7 @@ int construct_dom0(struct domain *d) > #ifdef CONFIG_ARM_64 > else > { > + regs->cpsr = PSR_GUEST_INIT|PSR_MODE_EL1h; > /* From linux/Documentation/arm64/booting.txt */ > regs->x0 = kinfo.dtb_paddr; > regs->x1 = 0; /* Reserved for future use */ > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > index 5181e7b..2c20821 100644 > --- a/xen/include/asm-arm/processor.h > +++ b/xen/include/asm-arm/processor.h > @@ -46,6 +46,8 @@ > #define SCTLR_BASE 0x00c50078 > #define HSCTLR_BASE 0x30c51878 > > +#define PSR_GUEST_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK) > + > /* HCR Hyp Configuration Register */ > #define HCR_TGE (1<<27) > #define HCR_TVM (1<<26) > diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h > index 8aa62d3..cea12b2 100644 > --- a/xen/include/public/arch-arm.h > +++ b/xen/include/public/arch-arm.h > @@ -237,8 +237,6 @@ typedef uint64_t xen_callback_t; > #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */ > #define PSR_JAZELLE (1<<24) /* Jazelle Mode */ > > -#define PSR_GUEST_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC) > - > #endif /* __XEN_PUBLIC_ARCH_ARM_H__ */ > > /* >