From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH v2 2/3] Nested VMX: Clear bit 31 of IA32_VMX_BASIC MSR Date: Tue, 10 Sep 2013 09:51:19 +0100 Message-ID: <522EDD87.4030401@citrix.com> References: <1378793667-6694-1-git-send-email-yang.z.zhang@intel.com> <1378793667-6694-3-git-send-email-yang.z.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1378793667-6694-3-git-send-email-yang.z.zhang@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Yang Zhang Cc: xen-devel@lists.xensource.com, eddie.dong@intel.com, JBeulich@suse.com List-Id: xen-devel@lists.xenproject.org On 10/09/13 07:14, Yang Zhang wrote: > From: Yang Zhang > > The bit 31 of revision_id will set to 1 if vmcs shadowing enabled. And > according intel SDM, the bit 31 of IA32_VMX_BASIC MSR is always 0. So we > cannot set low 32 bit of IA32_VMX_BASIC to revision_id directly. Must clear > the bit 31 to 0. > > Signed-off-by: Yang Zhang Reviewed-by: Andrew Cooper > --- > xen/arch/x86/hvm/vmx/vvmx.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c > index c6c8b88..122462f 100644 > --- a/xen/arch/x86/hvm/vmx/vvmx.c > +++ b/xen/arch/x86/hvm/vmx/vvmx.c > @@ -1847,7 +1847,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) > switch (msr) { > case MSR_IA32_VMX_BASIC: > data = (host_data & (~0ul << 32)) | > - ((v->arch.hvm_vmx.vmcs)->vmcs_revision_id); > + (v->arch.hvm_vmx.vmcs->vmcs_revision_id & 0x7fffffff); > break; > case MSR_IA32_VMX_PINBASED_CTLS: > case MSR_IA32_VMX_TRUE_PINBASED_CTLS: