From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH RFC 6/7] xen: arm: configure TCR_EL2 for 40 bit physical address space Date: Wed, 18 Sep 2013 16:50:38 +0100 Message-ID: <5239CBCE.9050008@linaro.org> References: <1379381846.11304.73.camel@hastur.hellion.org.uk> <1379382050-11821-6-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1379382050-11821-6-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: julien.grall@citrix.com, stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 09/17/2013 02:40 AM, Ian Campbell wrote: > Signed-off-by: Ian Campbell Acked-by: Julien Grall > --- > xen/arch/arm/arm64/head.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S > index 6406562..59cbcd8 100644 > --- a/xen/arch/arm/arm64/head.S > +++ b/xen/arch/arm/arm64/head.S > @@ -200,12 +200,12 @@ skip_bss: > msr mair_el2, x0 > > /* Set up the HTCR: > - * PASize -- 4G > + * PASize -- 40 bits / 1TB > * Top byte is used > * PT walks use Outer-Shareable accesses, > * PT walks are write-back, write-allocate in both cache levels, > * Full 64-bit address space goes through this table. */ > - ldr x0, =0x80802500 > + ldr x0, =0x80822500 > msr tcr_el2, x0 > > /* Set up the SCTLR_EL2: > -- Julien Grall