From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH v2 06/13] x86/PMU: Add public xenpmu.h Date: Mon, 30 Sep 2013 09:25:55 -0400 Message-ID: <52497BE3.9090206@oracle.com> References: <1379670132-1748-1-git-send-email-boris.ostrovsky@oracle.com> <1379670132-1748-7-git-send-email-boris.ostrovsky@oracle.com> <5243097802000078000F6480@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1VQdS4-0005no-Qm for xen-devel@lists.xenproject.org; Mon, 30 Sep 2013 13:23:53 +0000 In-Reply-To: <5243097802000078000F6480@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: suravee.suthikulpanit@amd.com, George.Dunlap@eu.citrix.com, jacob.shin@amd.com, eddie.dong@intel.com, dietmar.hahn@ts.fujitsu.com, jun.nakajima@intel.com, xen-devel List-Id: xen-devel@lists.xenproject.org On 09/25/2013 10:04 AM, Jan Beulich wrote: >>>> On 20.09.13 at 11:42, Boris Ostrovsky wrote: >> +struct amd_vpmu_context { >> + uint64_t counters[XENPMU_AMD_MAX_COUNTERS]; >> + uint64_t ctrls[XENPMU_AMD_MAX_COUNTERS]; >> + uint8_t msr_bitmap_set; /* Used by HVM only */ >> +}; > sizeof() this will not be the same for this in a 64-bit an a 32-bit guest. > Are you intentionally creating a need for translation here? > >> + >> +/* Intel PMU registers and structures */ >> +#define XENPMU_CORE2_MAX_ARCH_PMCS 16 >> +#define XENPMU_CORE2_MAX_FIXED_PMCS 4 >> +struct core2_vpmu_context { >> + uint64_t global_ctrl; >> + uint64_t global_ovf_ctrl; >> + uint64_t global_status; >> + uint64_t global_ovf_status; >> + uint64_t fixed_ctrl; >> + uint64_t ds_area; >> + uint64_t pebs_enable; >> + uint64_t debugctl; >> + uint64_t fix_counters[XENPMU_CORE2_MAX_FIXED_PMCS]; >> + struct { >> + uint64_t counter; >> + uint64_t control; >> + } arch_msr_pair[XENPMU_CORE2_MAX_ARCH_PMCS]; >> +}; > I realize that using embedded arrays in both AMD and Intel > structures makes things easier to implement, but it reduces > forward compatibility. I'd therefore prefer those to be made > handles. (I missed this comment earlier). This is not done because it's easier but because I need to keep the structure in a shared page. -boris