From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: ARM GIC Security Extensions and Xen Date: Mon, 28 Oct 2013 08:00:40 -0700 Message-ID: <526E7C18.5040208@linaro.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Mj Embd , "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org On 10/28/2013 04:29 AM, Mj Embd wrote: > Slight modification GICC_AIAR (%s/GICV/GICC/g) > > On Mon, Oct 28, 2013 at 4:57 PM, Mj Embd wrote: >> Does Xen GIC implementation use Grp0 as secure and Grp 1 as NS as >> mentioned in GIC 400 manual >> -- >> When a GIC that implements the GIC Security Extensions is connected to >> a processor that implements the ARM Security Extensions: >> >> Group 0 interrupts are Secure interrupts, and Group 1 interrupts are >> Non-secure interrupts. >> >> >> ARM IHI 0048B.b Non-Confidential ID072613 Pg 1-16 >> --- >> >> The manual also states >> >> In GICv2, ARM recommends that separate registers are used to manage >> Group 0 and Group 1 interrupts: >> >> GICV_IAR, GICV_EOIR, and GICV_HPPIR for Group 0 interrupts GICV_AIAR, >> GICV_AEOIR, and GICV_AHPPIR for Group 1 interrupts. >> >> pg 5-162 >> >> >> I was not able to find GICV_AIAR being used in code. Xen is running in non-secure mode. The register GICC_AIAR is only used for secure mode. Actually in secure mode, it's an alias to GICC_IAR. -- Julien Grall