From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-1?Q?Roger_Pau_Monn=E9?= Subject: Re: [PATCH RFC] pvh: clearly specify used parameters in vcpu_guest_context Date: Sat, 16 Nov 2013 09:04:52 +0100 Message-ID: <52872724.6070502@citrix.com> References: <1384530622-31703-1-git-send-email-roger.pau@citrix.com> <52865AC60200007800103AAE@nat28.tlf.novell.com> <20131115165509.GA58145@deinos.phlegethon.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1VhasB-0007Ev-An for xen-devel@lists.xenproject.org; Sat, 16 Nov 2013 08:04:55 +0000 In-Reply-To: <20131115165509.GA58145@deinos.phlegethon.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Tim Deegan , Jan Beulich Cc: George Dunlap , xen-devel@lists.xenproject.org, Keir Fraser List-Id: xen-devel@lists.xenproject.org On 15/11/13 17:55, Tim Deegan wrote: > At 16:32 +0000 on 15 Nov (1384529574), Jan Beulich wrote: >>>>> On 15.11.13 at 16:50, Roger Pau Monne wrote: >>> --- a/xen/arch/x86/domain.c >>> +++ b/xen/arch/x86/domain.c >>> @@ -704,9 +704,11 @@ int arch_set_info_guest( >>> /* PVH 32bitfixme */ >>> ASSERT(!compat); >>> >>> - if ( c(ctrlreg[1]) || c(ldt_base) || c(ldt_ents) || >>> + if ( c(ctrlreg[0]) || c(ctrlreg[1]) || c(ctrlreg[2]) || >>> + c(ctrlreg[4]) || c(ldt_base) || c(ldt_ents) || >> >> I think it should actually be a bug for the guest to request an >> all blank CR0 or CR4. Minimally CR0.PE, CR0.PG, and CR4.PAE >> would seem to be a valid requirement to be set. > > I think zero is better. Guest CRx are explicitly _not_ loaded from > these fields so making them look like valid CRx values is just confusing. > > But even better would be to allow all these fields to be set to any > valid values, and to load the state into the guest vCPU. I think > that's going to be more sensible once the current restriction that PVH > vCPUs are always in long more goes away. Ack, I'm going to rework the patch in order to check and load the other control registers.