From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v2 06/15] xen: arm64: Map xgene PCI memory regions and interrupts to dom0. Date: Fri, 22 Nov 2013 16:59:55 +0000 Message-ID: <528F8D8B.2070808@linaro.org> References: <1385137474-31245-6-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1385137474-31245-6-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel@lists.xen.org Cc: pranavkumar@linaro.org, tim@xen.org, Anup Patel , stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Can you add a comment to specify that for the future we plan to support PCI for all platforms ? (ie this patch a kind of "WORKAROUND" for now) On 11/22/2013 04:24 PM, Ian Campbell wrote: > Signed-off-by: Ian Campbell > --- > v2: This replaces "HACK: xen: arm: map PCI controller ranges region MMIOs to > dom0." > --- > xen/arch/arm/platforms/xgene-storm.c | 76 ++++++++++++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > > diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c > index 8658996..f3cc51b 100644 > --- a/xen/arch/arm/platforms/xgene-storm.c > +++ b/xen/arch/arm/platforms/xgene-storm.c > @@ -24,12 +24,87 @@ > #include > #include > #include > +#include > > static uint32_t xgene_storm_quirks(void) > { > return PLATFORM_QUIRK_DOM0_MAPPING_11|PLATFORM_QUIRK_GIC_64K_STRIDE; > } > > +static int map_one_mmio(struct domain *d, const char *what, > + paddr_t start, paddr_t end) > +{ > + int ret; > + > + printk("Additional MMIO %"PRIpaddr"-%"PRIpaddr" (%s)\n", > + start, end, what); > + ret = map_mmio_regions(d, start, end, start); > + if ( ret ) > + printk("Failed to map %s @ %"PRIpaddr" to dom%d\n", > + what, start, d->domain_id); > + return ret; > +} > + > +static int map_one_spi(struct domain *d, const char *what, > + unsigned int spi, unsigned int type) > +{ > + struct dt_irq irq; > + int ret; > + > + irq.type = type; > + > + irq.irq = spi + 32; /* SPIs start at IRQ 32 */ > + > + printk("Additional IRQ %u (%s)\n", irq.irq, what); > + > + ret = gic_route_irq_to_guest(d, &irq, what); > + if ( ret ) > + printk("Failed to route %s to dom%d\n", what, d->domain_id); > + > + return ret; > +} > + > +static int xgene_storm_specific_mapping(struct domain *d) > +{ > + int ret; > + > + /* Map the PCIe bus resources */ > + ret = map_one_mmio(d, "PCI MEM REGION", 0xe000000000UL, 0xe010000000UL); > + if ( ret ) > + goto err; > + > + ret = map_one_mmio(d, "PCI IO REGION", 0xe080000000UL, 0xe080010000UL); > + if ( ret ) > + goto err; > + > + ret = map_one_mmio(d, "PCI CFG REGION", 0xe0d0000000UL, 0xe0d0200000UL); > + if ( ret ) > + goto err; > + ret = map_one_mmio(d, "PCI MSI REGION", 0xe010000000UL, 0xe010800000UL); > + if ( ret ) > + goto err; > + > + ret = map_one_spi(d, "PCI#INTA", 0xc2, DT_IRQ_TYPE_LEVEL_HIGH); > + if ( ret ) > + goto err; > + > + ret = map_one_spi(d, "PCI#INTB", 0xc3, DT_IRQ_TYPE_LEVEL_HIGH); > + if ( ret ) > + goto err; > + > + ret = map_one_spi(d, "PCI#INTC", 0xc4, DT_IRQ_TYPE_LEVEL_HIGH); > + if ( ret ) > + goto err; > + > + ret = map_one_spi(d, "PCI#INTD", 0xc5, DT_IRQ_TYPE_LEVEL_HIGH); > + if ( ret ) > + goto err; > + > + ret = 0; > +err: > + return ret; > +} > + > > static const char const *xgene_storm_dt_compat[] __initdata = > { > @@ -40,6 +115,7 @@ static const char const *xgene_storm_dt_compat[] __initdata = > PLATFORM_START(xgene_storm, "APM X-GENE STORM") > .compatible = xgene_storm_dt_compat, > .quirks = xgene_storm_quirks, > + .specific_mapping = xgene_storm_specific_mapping, > .dom0_evtchn_ppi = 24, > PLATFORM_END > > -- Julien Grall