From mboxrd@z Thu Jan 1 00:00:00 1970 From: George Dunlap Subject: Re: [PATCH V8] ns16550: Add support for UART present in Broadcom TruManage capable NetXtreme chips Date: Fri, 6 Dec 2013 16:00:44 +0000 Message-ID: <52A1F4AC.6020506@eu.citrix.com> References: <1386283126-2045-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <52A19BC8020000780010ABFC@nat28.tlf.novell.com> <52A1F2B9.2070504@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <52A1F2B9.2070504@amd.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Aravind Gopalakrishnan , Jan Beulich , xen-devel@lists.xen.org Cc: Thomas Lendacky , Andrew Cooper , shurd@broadcom.com, Suravee Suthikulpanit , Sherry Hurwitz List-Id: xen-devel@lists.xenproject.org On 12/06/2013 03:52 PM, Aravind Gopalakrishnan wrote: > On 12/6/2013 2:41 AM, Jan Beulich wrote: >>>>> On 05.12.13 at 23:38, Aravind Gopalakrishnan >>>>> wrote: >>> Since it is an MMIO device, the code has been modified to accept >>> MMIO based >>> devices as well. MMIO device settings are populated in the >>> 'uart_config' >>> table. >>> It also advertises 64 bit BAR. Therefore, code is reworked to >>> account for 64 >>> bit BAR and 64 bit MMIO lengths. >>> >>> Some more quirks are - the need to shift the register offset by a >>> specific >>> value and we also need to verify (UART_LSR_THRE && UART_LSR_TEMT) >>> bits before >>> transmitting data. >>> >>> While testing, include com1=115200,8n1,pci,0 on the xen cmdline to >>> observe >>> output on console using SoL. >>> >>> Changes from V7: >>> - per Jan's comments: >>> - Moving pci_ro_device to ns16550_init_postirq() so that either >>> one of pci_hide_device or pci_ro_device is done at one place >>> - remove leading '0' from printk as absent segment identifier >>> implies zero anyway. >>> - per Ian's comments: >>> - fixed issues that casued his build to fail. >>> - cross-compiled for arm32 and arm64 after applying patch and >>> build was successful on local machine. >>> >>> Signed-off-by: Aravind Gopalakrishnan >>> Signed-off-by: Suravee Suthikulpanit >>> Signed-off-by: Thomas Lendacky >> I'm fine with this now, but I take it that you're not intending this >> to go into 4.4, or else you'd have Cc-ed George explaining why >> a freeze exception is being requested. >> >> > Thanks Jan, > > (Now cc-ing George..) > Please do consider this patch for 4.4 as it is a customer request for > the AMD Open Compute project. Can you take a look at the guidelines linked below, think about the questions there, and then give a brief summary of the benefits and potential risks? http://wiki.xen.org/wiki/Xen_Roadmap/4.4#Exception_guidelines_for_after_the_code_freeze Thanks, -George