From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v1 0/2] xen/arm: maintenance_interrupt SMP fix Date: Mon, 27 Jan 2014 17:51:56 +0000 Message-ID: <52E69CBC.3090207@linaro.org> References: <1390844023-23123-1-git-send-email-oleksandr.tyshchenko@globallogic.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1390844023-23123-1-git-send-email-oleksandr.tyshchenko@globallogic.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Oleksandr Tyshchenko Cc: Stefano Stabellini , Ian Campbell , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 01/27/2014 05:33 PM, Oleksandr Tyshchenko wrote: > Hi, all. Hello Oleksandr, > We are trying to bringing up XEN on DRA7XX (OMAP5) platform. > > We sometimes see some hangs in Hypervisor and these hangs are related to SMP. > We found out that deadlock took place in on_selected_cpus function > in case of simultaneous occurrence cross-interrupts. > > The issue: > > 1. We receive irqs from first CPU (for example CPU0) and second CPU (for example CPU1) in parallel. > 2. In our case the maintenance_interrupt function for maintenance irq from CPU0 is executed on CPU1 and > maintenance_interrupt for irq from CPU1 is executed on CPU0. > 3. According to existing logic we have run gic_irq_eoi function on CPU which it was scheduled. gic_irq_eoi is only called for physical IRQ routed to the guest (eg: hard drive, network, ...). As far as I remember, these IRQs are only routed to CPU0. Do you pass-through PPIs to dom0? -- Julien Grall