From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v1 0/2] xen/arm: maintenance_interrupt SMP fix Date: Wed, 29 Jan 2014 13:12:05 +0000 Message-ID: <52E8FE25.1050108@linaro.org> References: <1390844023-23123-1-git-send-email-oleksandr.tyshchenko@globallogic.com> <52E69CBC.3090207@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Oleksandr Tyshchenko Cc: Stefano Stabellini , Ian Campbell , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org Hello Oleksandr, On 28/01/14 19:25, Oleksandr Tyshchenko wrote: [..] > > Do you pass-through PPIs to dom0? > > If I understand correctly that PPIs is irqs from 16 to 31. > So yes, I do. I see timer's irqs and maintenance irq which routed to > both CPUs. This IRQs are used by Xen, therefore they are emulated for dom0 and domU. Xen won't EOI in maintenance_interrupt theses IRQs. > > And I have printed all irqs which fall to gic_route_irq_to_guest and > gic_route_irq functions. > ... > (XEN) GIC initialization: > (XEN) gic_dist_addr=0000000048211000 > (XEN) gic_cpu_addr=0000000048212000 > (XEN) gic_hyp_addr=0000000048214000 > (XEN) gic_vcpu_addr=0000000048216000 > (XEN) gic_maintenance_irq=25 > (XEN) GIC: 192 lines, 2 cpus, secure (IID 0000043b). > (XEN) > (XEN) >>>>> gic_route_irq: irq: 25, cpu_mask: 00000001 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 30, cpu_mask: 00000001 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 26, cpu_mask: 00000001 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 27, cpu_mask: 00000001 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 104, cpu_mask: 00000001 > (XEN) Using scheduler: SMP Credit Scheduler (credit) > (XEN) Allocated console ring of 16 KiB. > (XEN) VFP implementer 0x41 architecture 4 part 0x30 variant 0xf rev 0x0 > (XEN) Bringing up CPU1 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 25, cpu_mask: 00000002 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 30, cpu_mask: 00000002 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 26, cpu_mask: 00000002 > (XEN) > (XEN) >>>>> gic_route_irq: irq: 27, cpu_mask: 00000002 > (XEN) CPU 1 booted. > (XEN) Brought up 2 CPUs > (XEN) *** LOADING DOMAIN 0 *** > (XEN) Populate P2M 0xc8000000->0xd0000000 (1:1 mapping for dom0) > (XEN) > (XEN) >>>>> gic_route_irq_to_guest: domid: 0, irq: 61, cpu: 0 [..] > (XEN) >>>>> gic_route_irq_to_guest: domid: 1, irq: 61, cpu: 1 Not related to this patch series, but is it normal that you passthrough the same interrupt both to dom0 and domU? There is few other case like that. -- Julien Grall