From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH-4.5 3/4] xen/arm: do not request maintenance_interrupts Date: Mon, 10 Feb 2014 17:11:04 +0000 Message-ID: <52F90828.4060809@linaro.org> References: <1391799378-31664-3-git-send-email-stefano.stabellini@eu.citrix.com> <52F567CB.7080302@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini Cc: julien.grall@citrix.com, xen-devel@lists.xensource.com, Ian.Campbell@citrix.com List-Id: xen-devel@lists.xenproject.org On 02/10/2014 05:06 PM, Stefano Stabellini wrote: > On Fri, 7 Feb 2014, Julien Grall wrote: >> On 07/02/14 18:56, Stefano Stabellini wrote: >> > +static void gic_clear_lrs(struct vcpu *v) >>> +{ >>> + struct pending_irq *p; >>> + int i = 0, irq; >>> + uint32_t lr; >>> + bool_t inflight; >>> + >>> + ASSERT(!local_irq_is_enabled()); >>> + >>> + while ((i = find_next_bit((const long unsigned int *) >>> &this_cpu(lr_mask), >>> + nr_lrs, i)) < nr_lrs) { >> >> Did you look at to ELRSR{0,1} registers which list the usable LRs? I think you >> can use it with the this_cpu(lr_mask) to avoid browsing every LRs. > > Given that we only have 4 LR registers, I think that unconditionally > reading 2 ELRSR registers would cost more than simply checking lr_mask > on average. The maximum number of LR registers is 64. I agree that the current hardwares only handle 4 ... but we should think about future hardware. -- Julien Grall