From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: VM Feature levelling improvements proposal (draft C)
Date: Tue, 18 Feb 2014 17:57:34 +0000
Message-ID: <53039F0E.8010302@citrix.com>
References: <53023729.7020009@citrix.com> <53038D7A.8030807@oracle.com>
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To: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Keir Fraser <keir@xen.org>, Jun Nakajima <jun.nakajima@intel.com>, Tim Deegan <tim@xen.org>, Xen-devel List <xen-devel@lists.xen.org>, Jan Beulich <JBeulich@suse.com>, SuraveeSuthikulpanit <suravee.suthikulpanit@amd.com>, "xiantao.zhang@intel.com" <xiantao.zhang@intel.com>
List-Id: xen-devel@lists.xenproject.org

On 18/02/14 16:42, Boris Ostrovsky wrote:
> On 02/17/2014 11:22 AM, Andrew Cooper wrote:
>> Hello,
>>
>> Here is a design proposal to improve VM feature levelling support in Xen
>> and libxc.
>
> In case you haven't seen this you might also find this useful:
> http://developer.amd.com/wordpress/media/2012/10/CrossVendorMigration.pdf
>
> It's a slightly different subject but perhaps some of the experiences
> that are listed there could influence your design.
>
> -boris

I had read that as part of preparing this.  It appears to be HVM
specific, which makes the feature reporting, as Xen can report any
information it likes in all circumstances.

>>From the point of view of a domain configuration, I absolutely still
want things like

cpuid = [ '0:eax=0x3,ebx=0x0,ecx=0x0,edx=0x0',
          '1:eax=0x0f61,
             ecx=xxxxxxxx0xx00xxxxxxxxx0xxxxxxxxx,
             edx=xxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxx',
          '0x80000000:eax=0x80000004,ebx=0x0,ecx=0x0,edx=0x0',
          '0x80000001:eax=0x0f61,
                      ecx=xxxxxxxxxxxxxxxxxx0000000000000x,
                      edx=00xx000xx0xxx0xxxxxxxxxxxxxxxxxx']

to work, albeit with rather more reality enforced.  The main point of
this proposal is to also make it work for PV guests, at least as far as
the feature leaves are concerned.


On that note, I do have a question for anyone from AMD who might know
the answer.

AMD has the CPUID override MSRs 0xc001100{4,5} which cover the basic and
extended feature leaves.  Are there any MSRs to cover
CPUID.0000_000D[ecx=1].eax which contains the 'XSAVEOPT' bit, or
CPUID.0000_0007[ecx=1].ebx which is the "structured extended" feature
map?  I cant find any reference to new override MSRs in the manuals (or
with google), or to having cpuid faulting support like Intel cpus.

~Andrew