Re: Bringing up sequence for non-boot CPU fails

[Julien Grall <julien.grall@linaro.org>]

Hello Andrii and Oleksandr,

Sorry for the late answer.

On 19/02/14 20:35, Andrii Anisov wrote:
> The latest update is: Oleksandr tried solution suggested by Julien and
> the issue seems to be not reproducible.

Thanks for the update. I talked with Ian about this issue, the problem 
may come from setup_pagetables (arch/arm/mm.c).
The function is zeros boot_pgtable, boot_first and boot_second, then 
just clean the cache for theses ranges.
But ... when the secondary CPU sets up theses variables, the cache is 
disabled. When the cache is enabled (just before we enable paging), 
cache may contain data that was not reached the memory, therefore it 
will shadow the real data.

Can you try these 2 small tests (separately):
   - Flush all the cache before boot_pgtable is zeroed (arch/arm/mm.c:486)
   - Flush all the cache after clean_xen_dcache(boot_second) 
(arch/arm/mm.c:493)

If the former test is failing and not the latter, then we have found the 
issue :).

I think the 3 clean_xen_dcache should be replaced by a clean and 
invalidate dcache.

Regards,

-- 
Julien Grall