From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Keir Fraser <keir@xen.org>,
Ian Campbell <ian.campbell@citrix.com>,
Ian Jackson <Ian.Jackson@eu.citrix.com>,
Donald D Dugger <donald.d.dugger@intel.com>,
Jun Nakajima <jun.nakajima@intel.com>,
xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH 2/3] x86/idle: update to include further package/core residency MSRs
Date: Wed, 05 Mar 2014 10:30:14 -0500 [thread overview]
Message-ID: <53174306.4080502@oracle.com> (raw)
In-Reply-To: <53174D980200007800121377@nat28.tlf.novell.com>
On 03/05/2014 10:15 AM, Jan Beulich wrote:
>>>> On 05.03.14 at 16:07, Boris Ostrovsky <boris.ostrovsky@oracle.com> wrote:
>> On 03/05/2014 05:37 AM, Jan Beulich wrote:
>>> With the number of these growing it becomes increasingly desirable to
>>> not repeatedly alter the sysctl interface to accommodate them. Replace
>>> the explicit listing of numbered states by arrays, unused fields of
>>> which will remain untouched by the hypercall.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>>
>>> --- 2014-02-13.orig/tools/libxc/xc_pm.c 2014-03-04 17:43:06.000000000 +0100
>>> +++ 2014-02-13/tools/libxc/xc_pm.c 2014-03-05 08:54:58.000000000 +0100
>>> @@ -123,46 +123,90 @@ int xc_pm_get_max_cx(xc_interface *xch,
>>>
>>> int xc_pm_get_cxstat(xc_interface *xch, int cpuid, struct xc_cx_stat *cxpt)
>>> {
>>> - DECLARE_SYSCTL;
>>> - DECLARE_NAMED_HYPERCALL_BOUNCE(triggers, cxpt->triggers, 0, XC_HYPERCALL_BUFFER_BOUNCE_BOTH);
>>> - DECLARE_NAMED_HYPERCALL_BOUNCE(residencies, cxpt->residencies, 0, XC_HYPERCALL_BUFFER_BOUNCE_BOTH);
>>> + uint64_t pc[7], cc[7];
>> Do you need pc[10]? There seem to exist pc8-10 states (at least there
>> are references to them below for Haswell).
> Did you not realize that this is the compatibility wrapper around the
> new function? There's no place for me to store pc8 and higher, so
> why would I waste space to retrieve them from the hypervisor?
No, I didn't realize this (but now I see it).
>
>>> @@ -1950,8 +1950,22 @@ struct xc_cx_stat {
>>> };
>>> typedef struct xc_cx_stat xc_cx_stat_t;
>>>
>>> +struct xc_cx_stat_v2 {
>>> + uint32_t nr; /* entry nr in triggers[]/residencies[], incl C0 */
>>> + uint32_t last; /* last Cx state */
>>> + uint64_t idle_time; /* idle time from boot */
>>> + uint64_t *triggers; /* Cx trigger counts */
>>> + uint64_t *residencies; /* Cx residencies */
>>> + uint32_t nr_pc; /* entry nr in pc[] */
>>> + uint32_t nr_cc; /* entry nr in cc[] */
>> Are these entry number or number of entries (or largest entry number) in
>> appropriate array?
> Just like above (for "nr") - the number of entries in the arrays.
>
>>> + uint64_t *pc; /* 1-biased indexing (i.e. excl C0) */
>>> + uint64_t *cc; /* 1-biased indexing (i.e. excl C0) */
> The slightly unusual thing is the indexing into these array: entry 0
> has data for C1, entry 1 for C2, etc.
This I understand. I just think that "entry nr" (especially the the fact
that the first word is in singular) is confusing. Including the comment
for the first member.
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
next prev parent reply other threads:[~2014-03-05 15:28 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-05 10:34 [PATCH 0/3] x86: support further Intel CPU families Jan Beulich
2014-03-05 10:36 ` [PATCH 1/3] " Jan Beulich
2014-03-18 2:44 ` Tian, Kevin
2014-03-05 10:37 ` [PATCH 2/3] x86/idle: update to include further package/core residency MSRs Jan Beulich
2014-03-05 10:42 ` Jan Beulich
2014-03-18 2:44 ` Tian, Kevin
2014-03-05 15:07 ` Boris Ostrovsky
2014-03-05 15:15 ` Jan Beulich
2014-03-05 15:30 ` Boris Ostrovsky [this message]
2014-03-13 14:11 ` Ian Campbell
2014-03-13 14:27 ` Jan Beulich
2014-03-13 15:34 ` Ian Campbell
2014-03-13 15:48 ` Jan Beulich
2014-03-13 15:53 ` Ian Campbell
2014-03-18 16:18 ` Ian Jackson
2014-03-18 16:25 ` Jan Beulich
2014-03-13 14:28 ` Keir Fraser
2014-03-05 10:37 ` [PATCH 3/3] xenpm: use new Cx statistics interface Jan Beulich
2014-03-05 15:47 ` Boris Ostrovsky
2014-03-05 15:53 ` Jan Beulich
2014-03-05 17:05 ` Boris Ostrovsky
2014-03-06 9:37 ` Jan Beulich
2014-03-13 14:12 ` Ian Campbell
2014-03-18 2:45 ` Tian, Kevin
2014-03-12 9:38 ` Ping: [PATCH 0/3] x86: support further Intel CPU families Jan Beulich
2014-03-12 10:18 ` Ian Campbell
2014-03-17 13:28 ` [PATCH v2 0/2] " Jan Beulich
2014-03-17 13:38 ` [PATCH v2 1/2] x86: Intel CPU family update Jan Beulich
2014-03-17 13:39 ` [PATCH v2 2/2] x86/idle: update to include further package/core residency MSRs Jan Beulich
2014-03-17 13:43 ` Ian Campbell
2014-03-17 15:48 ` Jan Beulich
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