From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH v2 0/4] Expose HW APIC virtualization support to HVM guests Date: Tue, 11 Mar 2014 10:32:36 -0400 Message-ID: <531F1E84.3030603@oracle.com> References: <1394510043-3159-1-git-send-email-boris.ostrovsky@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "Zhang, Yang Z" Cc: "keir@xen.org" , "jbeulich@suse.com" , "stefano.stabellini@eu.citrix.com" , "Dong, Eddie" , "ian.jackson@eu.citrix.com" , "xen-devel@lists.xen.org" , "Nakajima, Jun" , "ian.campbell@citrix.com" List-Id: xen-devel@lists.xenproject.org On 03/11/2014 03:37 AM, Zhang, Yang Z wrote: > Boris Ostrovsky wrote on 2014-03-11: >> Version 2: >> * Added ability to specify hypervisor CPUID leaves in config file (this requires >> new sysctl) >> * Use 2 bits to indicate what is supported --- one for APIC memory access and >> the >> other for x2APIC. Still not sure whether virtual interrupt delivery should be >> exposed as well. >> >> ... >> >> I am also not sure whether (cpu_has_vmx_apic_reg_virt & >> cpu_has_vmx_virtualize_x2apic_mode) is sufficient to declare full HW >> APIC support to a guest. The tests show ~95K VMEXITs when virtual > The former is enough. Hardware has APICv must have the virtualize x2apic too. > >> interrupt delivery and posted interrupts are turned off so there >> appears to still be some benefit. I suppose we can use another CPUID >> bit for these two (although I am not particularly eager to do this). > The three features are coexisting. I think you can use one bit to show them. As I learned yesterday (the hard way) this is not necessarily the case. I was testing this on a laptop that has MSR 0x48b (MSR_IA32_VMX_PROCBASED_CTLS2) return 0x8ff00000000: yes for x2APIC virtualization but no for APIC register access virtualization. Which is why I added another bit to distinguish the two Thanks. -boris