From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH for-4.5 7/8] xen/irq: Handle multiple action per IRQ Date: Tue, 18 Mar 2014 12:26:53 +0000 Message-ID: <53283B8D.4030401@linaro.org> References: <1390581822-32624-1-git-send-email-julien.grall@linaro.org> <1390581822-32624-8-git-send-email-julien.grall@linaro.org> <1392810905.29739.19.camel@kazak.uk.xensource.com> <530673BD.9010301@linaro.org> <530B5275.7010008@citrix.com> <530B6606020000780011ED39@nat28.tlf.novell.com> <530B5BAC.2010100@linaro.org> <531F28D5.1000901@linaro.org> <531F431D0200007800122EC3@nat28.tlf.novell.com> <53276389.8080109@linaro.org> <1395135184.12847.1.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WPt6f-00007a-Nl for xen-devel@lists.xenproject.org; Tue, 18 Mar 2014 12:26:57 +0000 Received: by mail-wi0-f176.google.com with SMTP id hr14so3576403wib.15 for ; Tue, 18 Mar 2014 05:26:56 -0700 (PDT) In-Reply-To: <1395135184.12847.1.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: Keir Fraser , patches@linaro.org, Stefano Stabellini , tim@xen.org, stefano.stabellini@citrix.com, Jan Beulich , xen-devel@lists.xenproject.org List-Id: xen-devel@lists.xenproject.org Hi Ian, On 03/18/2014 09:33 AM, Ian Campbell wrote: > On Mon, 2014-03-17 at 21:05 +0000, Julien Grall wrote: >> For instance for the SMMU on midway, the device tree bindings is: >> >> smmu_sata: smmu@9,20180000 { >> compatible = "arm,mmu-400"; >> reg = <0x9 0x20180000 0x10000>; >> mmu-masters = <&sata 0 1 2 3 4 5 6 7 8 9>; >> #global-interrupts = <1>; >> interrupts = <0 114 4 0 114 4>; >> calxeda,smmu-secure-config-access; >> arm,smmu-isolate-devices; >> }; >> >> As you can see the same interrupts is used twice: > > Is that actually valid in device tree? Or is this a quirk of the midway > DT? Yes it's valid. The interrupts property for the SMMU is described as: "Interrupt list, with the first #global-irqs entries corresponding to the global interrupts and any following entries corresponding to context interrupts, specified in order of their indexing by the SMMU. For SMMUv2 implementations, there must be exactly one interrupt per context bank. In the case of a single, combined interrupt, it must be listed multiple times." On midway there is only one IRQ with is used for both context interrupt and global interrupt. As it's the only platform on Linux with SMMU support in the device tree, we don't know if every platform will have the same behavior. Regards, -- Julien Grall