From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
To: Jan Beulich <jbeulich@suse.com>,
"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: Ian.Jackson@eu.citrix.com, Keir Fraser <keir@xen.org>,
ian.campbell@citrix.com, "Suthikulpanit,
Suravee" <Suravee.Suthikulpanit@amd.com>,
"Hurwitz, Sherry" <sherry.hurwitz@amd.com>
Subject: Re: Fwd: [PATCH RFC 3/4] x86/AMD: support further feature masking MSRs
Date: Tue, 1 Apr 2014 18:10:42 -0500 [thread overview]
Message-ID: <533B4772.2020008@amd.com> (raw)
In-Reply-To: <CAAAAutDJ3CzvGp9jWCS7=b3rQsG81+w_W7qXLKxDWB7QBU23DQ@mail.gmail.com>
> Newer AMD CPUs also allow masking CPUID leaf 6 ECX and CPUID leaf 7
> sub-leaf 0 EAX and EBX.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com <mailto:jbeulich@suse.com>>
>
> TBD:
> - Fam15M0x is documented to not have MSR C0011002 despite
> CPUID[7,0].EBX != 0 from model 02
> onwards, and contrary to what I see on the system I have access to
> (which is model 02)
> - Fam12, Fam14, and Fam16 are documented to not have MSR C0011003
> despite CPUID[6].ECX != 0
Fam10 too has cpuid[6].ecx != 0 but no MSR C0011003
> - Fam11 is documented to not even have MSR C0011004 and C0011005
>
I am still trying to get some clarity on this;
Shall let you know soon :)
-Aravind.
next prev parent reply other threads:[~2014-04-01 23:10 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <532880230200007800125450@nat28.tlf.novell.com>
2014-03-19 9:16 ` [PATCH RFC 0/4] x86/AMD: support newer hardware features Jan Beulich
2014-03-19 9:46 ` [PATCH RFC 1/4] x86/SVM: support data breakpoint extension registers Jan Beulich
2014-03-19 9:47 ` [PATCH RFC 2/4] x86/PV: " Jan Beulich
2014-03-19 9:47 ` [PATCH RFC 3/4] x86/AMD: support further feature masking MSRs Jan Beulich
[not found] ` <CAAAAutDJ3CzvGp9jWCS7=b3rQsG81+w_W7qXLKxDWB7QBU23DQ@mail.gmail.com>
2014-04-01 23:10 ` Aravind Gopalakrishnan [this message]
2014-04-03 22:44 ` Fwd: " Aravind Gopalakrishnan
2014-04-04 9:37 ` Jan Beulich
2014-04-04 16:21 ` Aravind Gopalakrishnan
2014-04-07 6:54 ` Jan Beulich
2014-04-07 8:52 ` Andrew Cooper
2014-04-07 9:14 ` Jan Beulich
2014-03-19 9:48 ` [PATCH RFC 4/4] x86/AMD: clean up pre-canned family/revision handling for CPUID masking Jan Beulich
2014-03-26 14:13 ` [PATCH v2 RFC 2/4] x86/PV: support data breakpoint extension registers Jan Beulich
2014-03-27 15:28 ` Ian Campbell
2014-03-27 16:03 ` Jan Beulich
2014-03-27 16:23 ` Ian Campbell
2014-03-27 16:44 ` Jan Beulich
2014-03-27 17:29 ` Ian Campbell
2014-03-28 8:05 ` Jan Beulich
2014-03-28 9:55 ` Ian Campbell
2014-03-28 10:43 ` Jan Beulich
2014-03-28 10:56 ` Ian Campbell
2014-03-27 16:03 ` Andrew Cooper
2014-03-27 16:37 ` Jan Beulich
2014-03-27 17:11 ` Andrew Cooper
2014-03-28 10:46 ` Jan Beulich
[not found] ` <CAAAAutAgdSJqYEjc4dtixuTS2S=PUx-L4Sy=JCQRZ57rTdoPCQ@mail.gmail.com>
2014-03-26 22:35 ` [PATCH RFC 0/4] x86/AMD: support newer hardware features Aravind Gopalakrishnan
2014-04-01 23:10 ` Aravind Gopalakrishnan
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