From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH v4 3/6] xen: arm: flush TLB on all CPUs when
 setting or clearing fixmaps
Date: Thu, 03 Apr 2014 11:58:02 +0100
Message-ID: <533D3EBA.6060402@linaro.org>
References: <1396515560.4211.33.camel@kazak.uk.xensource.com>
	<1396515585-5737-3-git-send-email-ian.campbell@citrix.com>
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To: Ian Campbell <ian.campbell@citrix.com>
Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org
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On 04/03/2014 09:59 AM, Ian Campbell wrote:
> +/*
> + * Flush a range of VA's hypervisor mappings from the data TLB of all
> + * processors in the inner-shareable domain. This is not sufficient
> + * when changing code mappings or for self modifying code.
> + */
> +static inline void flush_xen_data_tlb_range_va(unsigned long va,
> +                                               unsigned long size)
> +{
> +    unsigned long end = va + size;
> +    dsb(sy); /* Ensure preceding are visible */
> +    while ( va < end ) {

Same error as the previous patch :):
while ( ... )
{

Except that:

Acked-by: Julien Grall <julien.grall@linaro.org>

Regards,

-- 
Julien Grall