From: Julien Grall <julien.grall@linaro.org>
To: Ian Campbell <ian.campbell@citrix.com>
Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org
Subject: Re: [PATCH v4 5/6] xen: arm: relax barriers in tlb flushes
Date: Thu, 03 Apr 2014 12:12:13 +0100 [thread overview]
Message-ID: <533D420D.3000806@linaro.org> (raw)
In-Reply-To: <1396515585-5737-5-git-send-email-ian.campbell@citrix.com>
On 04/03/2014 09:59 AM, Ian Campbell wrote:
> @@ -333,12 +333,12 @@ static inline void flush_xen_data_tlb_range_va(unsigned long va,
> unsigned long size)
> {
> unsigned long end = va + size;
> - dsb(sy); /* Ensure preceding are visible */
> + dsb(ish); /* Ensure preceding are visible */
I'm a bit lost with ish/nsh/sy/... shall we keep sy here?
flush_xen_data_tlb is used in iounmap and we want to make sure that
every write as been done just before.
Regards,
--
Julien Grall
next prev parent reply other threads:[~2014-04-03 11:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-03 8:59 [PATCH v4 0/6 ] xen: arm: smp & tlb cleanups Ian Campbell
2014-04-03 8:59 ` [PATCH v4 1/6] xen: arm: clarify naming of the Xen TLB flushing functions Ian Campbell
2014-04-03 8:59 ` [PATCH v4 2/6] xen: arm: consolidate body of flush_xen_data_tlb_range_va_local Ian Campbell
2014-04-03 10:56 ` Julien Grall
2014-04-03 8:59 ` [PATCH v4 3/6] xen: arm: flush TLB on all CPUs when setting or clearing fixmaps Ian Campbell
2014-04-03 10:58 ` Julien Grall
2014-04-03 8:59 ` [PATCH v4 4/6] xen: arm32: don't force the compiler to allocate a dummy register Ian Campbell
2014-04-03 8:59 ` [PATCH v4 5/6] xen: arm: relax barriers in tlb flushes Ian Campbell
2014-04-03 11:12 ` Julien Grall [this message]
2014-04-03 12:18 ` Ian Campbell
2014-04-03 12:42 ` Julien Grall
2014-04-03 8:59 ` [PATCH v4 6/6] xen: arm: relax barriers when flushing caches Ian Campbell
2014-04-03 12:55 ` Tim Deegan
2014-04-03 13:00 ` Ian Campbell
2014-04-03 16:29 ` [PATCH v4 0/6 ] xen: arm: smp & tlb cleanups Ian Campbell
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