From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH v2 13/15] xen/arm: Add support for GIC v3
Date: Thu, 10 Apr 2014 12:21:55 +0100
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To: Vijay Kilari <vijay.kilari@gmail.com>
Cc: Ian Campbell <Ian.Campbell@citrix.com>, Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Prasun Kapoor <Prasun.Kapoor@caviumnetworks.com>, Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>, xen-devel@lists.xen.org, Stefano Stabellini <stefano.stabellini@citrix.com>
List-Id: xen-devel@lists.xenproject.org

On 04/10/2014 12:06 PM, Vijay Kilari wrote:
> On Thu, Apr 10, 2014 at 4:04 PM, Julien Grall <julien.grall@linaro.org> wrote:
>> On 04/10/2014 11:00 AM, Ian Campbell wrote:
>>> On Fri, 2014-04-04 at 17:26 +0530, vijay.kilari@gmail.com wrote:
>>>
>>>> +#define gic_data_rdist_rd_base()        (this_cpu(rbase))
>>>> +#define gic_data_rdist_sgi_base()       (gic_data_rdist_rd_base() + SZ_64K)
>>>
>>> Macros should be SHOUTY and ideally a lot shorter.
>>>
>>> Since we have GICD[...] etc how about GICR[...]? And for the SGI bit
>>> just use GICR[GICR_SGI_...] (where GICR_SGI_ is 64K).
>>>
>>>> +
>>>> +static inline u64 read_cpuid_mpidr(void)
>>>> +{
>>>> +   return READ_SYSREG(MPIDR_EL1);
>>>> +}
>>>
>>> No need for this trivial wrapper.
>>
>> As said on V1:
>> MPDIR_EL1 is already replicated in current_cpu_data.mpidr.bits
>>
>   I find only MIDR register contents in current_cpu_data.midr.bits
> but not MPIDR

Second field of the structure...
Or even better cpu_logical_map(mycpu) as you already use in
gic_set_irq_property.

That made me think about your function gic_mpidir_to_affinity (see
below). Why do you mask with GICD_IROUTER_SPI_MODE_ANY? It should be
valid anywhere.

If not you may send the SGI to a wrong CPU.

+static u64 gic_mpidr_to_affinity(u64 mpidr)
+{
+    /* Make sure we don't broadcast the interrupt */
+    return mpidr & ~GICD_IROUTER_SPI_MODE_ANY;
+}
+

-- 
Julien Grall