From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: undefined instruction error during HYP mode switch
 for arndale-octa board
Date: Mon, 21 Apr 2014 13:39:18 +0100
Message-ID: <53551176.5070005@linaro.org>
References: <CAFpecnS+Rb8q8scAsWHVeN6-8qLWd51tyxFK0M=88qz_LNjH+Q@mail.gmail.com>
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To: HyonYoung Choi <commani@gmail.com>, Andre Przywara <andre.przywara@linaro.org>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Cc: Meng Xu <xumengpanda@gmail.com>
List-Id: xen-devel@lists.xenproject.org

Hello HyonYoung,

On 18/04/14 22:26, HyonYoung Choi wrote:
> I am trying to port xen to arndale-octa board.
>
> I am using u-boot modified for arndale-octa
> from tracking-arndale_octa branch of
> http://landing-teams/working/samsung/u-boot.git
>
> Because there is no HYP mode switch code in the u-boot,
> I tried to port your code in
> http://git.linaro.org/git/people/andre.przywara/u-boot.git.
> I also put debug code.
>
> In booting, it reboot infinitely with following error message:
> ======================
>     switch_hyp: GIC dist enabled
>    switch_hyp: 224 interrupts supportd
>    switch_hyp: all interrupts switched to non-secure
>    switch_hyp: setting SP start start address (0x9f86d6b4)
>    switch_hyp: kicked all CPUs
>    VBAR before: 0x9f86c000
> undefined instruction
> pc : [<9f86d748>]          lr : [<9f86d600>]
> sp : 9f7638c0  ip : 0000000f     fp : 9f86e4b4
> r10: 9f8ad294  r9 : 00000000     r8 : 9f763f10
> r7 : 00000000  r6 : ffffffff     r5 : 00000007  r4 : 9f86c000
> r3 : 10482000  r2 : 10480000     r1 : 016e3600  r0 : 00010000
> Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
> Resetting CPU ...
> ========================
>
> The problematic code is "mcr     p15, 0, r1, c1, c1, 2"
> in arch/arm/cpu/armv7/nonsec_virt.S , nonsec_init function
> Do you have any idea about this error?

U-boot is trying to write into NSCAR. This register is only writeable in 
Secure PL1 mode.

I suspect U-boot is running in non-secure mode. You may have the same 
problem as the odroid-xu where the SPL BL2 code brings up CPU in NS mode 
(see http://www.gossamer-threads.com/lists/xen/devel/325364#325364).

Regards,

-- 
Julien Grall