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From: Julien Grall <julien.grall@linaro.org>
To: Ian Campbell <Ian.Campbell@citrix.com>
Cc: julien.grall@citrix.com, xen-devel@lists.xensource.com,
	Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Subject: Re: [PATCH v7 05/12] xen/arm: nr_lrs should be uint8_t
Date: Wed, 23 Apr 2014 14:13:50 +0100	[thread overview]
Message-ID: <5357BC8E.8040007@linaro.org> (raw)
In-Reply-To: <1398258470.18537.99.camel@kazak.uk.xensource.com>

On 04/23/2014 02:07 PM, Ian Campbell wrote:
> On Wed, 2014-04-23 at 13:53 +0100, Julien Grall wrote:
>> On 04/23/2014 01:47 PM, Ian Campbell wrote:
>>> On Tue, 2014-04-08 at 16:12 +0100, Stefano Stabellini wrote:
>>>> A later patch is going to use uint8_t to keep track of LRs.
>>>> Both GICv3 and GICv2 don't need any more than an uint8_t to keep track
>>>> of the number of LRs.
>>>
>>> Did you confirm that this doesn't lead to inefficient loading and
>>> masking stuff on access?
>>>
>>>> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
>>>> Acked-by: Julien Grall <julien.grall@linaro.org>
>>>
>>> If yes then:
>>> Acked-by: Ian Campbell <ian.campbell@citrix.com>
>>>
>>> Although TBH I'm not sure why unsigned int was so harmful here.
>>
>> In struct irq_pending (see next patch: #6) the lr is stored using an uint8.
>>
>> IHMO, the both variable should have the same type to avoid mistake.
> 
> That could easily be avoided by a range check before setting nr_lrs,
> which we must have to do anyway.

We might want to check against the hardcoded value used to create gic_lr
(i.e 64).

For your sentence "Did you confirm that this doesn't lead to inefficient
loading and masking stuff on access?", there is an instruction to only
load/store 8 bits (strb, ldrb).
I don't see how the compiler will do inefficient loading.

-- 
Julien Grall

  reply	other threads:[~2014-04-23 13:13 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-08 15:11 [PATCH v7 0/12] remove maintenance interrupts Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 01/12] xen/arm: no need to set HCR_VI when using the vgic to inject irqs Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 02/12] xen/arm: remove unused virtual parameter from vgic_vcpu_inject_irq Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 03/12] xen/arm: set GICH_HCR_UIE if all the LRs are in use Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 04/12] xen/arm: support HW interrupts, do not request maintenance_interrupts Stefano Stabellini
2014-04-23 12:45   ` Ian Campbell
2014-04-23 12:54     ` Ian Campbell
2014-04-08 15:12 ` [PATCH v7 05/12] xen/arm: nr_lrs should be uint8_t Stefano Stabellini
2014-04-23 12:47   ` Ian Campbell
2014-04-23 12:53     ` Julien Grall
2014-04-23 13:07       ` Ian Campbell
2014-04-23 13:13         ` Julien Grall [this message]
2014-04-08 15:12 ` [PATCH v7 06/12] xen/arm: keep track of the GICH_LR used for the irq in struct pending_irq Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 07/12] xen/arm: s/gic_set_guest_irq/gic_raise_guest_irq Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 08/12] xen/arm: rename GIC_IRQ_GUEST_PENDING to GIC_IRQ_GUEST_QUEUED Stefano Stabellini
2014-04-23 12:52   ` Ian Campbell
2014-05-08 17:57     ` Stefano Stabellini
2014-05-09  8:33       ` Ian Campbell
2014-04-08 15:12 ` [PATCH v7 09/12] xen/arm: second irq injection while the first irq is still inflight Stefano Stabellini
2014-04-23 13:00   ` Ian Campbell
2014-04-08 15:12 ` [PATCH v7 10/12] xen/arm: don't protect GICH and lr_queue accesses with gic.lock Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 11/12] xen/arm: gic_events_need_delivery and irq priorities Stefano Stabellini
2014-04-23 13:31   ` Ian Campbell
2014-05-08 18:37     ` Stefano Stabellini
2014-05-09  8:37       ` Ian Campbell
2014-05-11 14:13         ` Stefano Stabellini
2014-05-11 16:50     ` Stefano Stabellini
2014-04-08 15:12 ` [PATCH v7 12/12] xen/arm: introduce GIC_PRI_TO_GUEST macro Stefano Stabellini
2014-04-23 13:32   ` Ian Campbell
2014-04-23 12:50 ` [PATCH v7 0/12] remove maintenance interrupts Julien Grall

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