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From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: "keir@xen.org" <keir@xen.org>,
	"Nakajima, Jun" <jun.nakajima@intel.com>,
	"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>,
	"Dong, Eddie" <eddie.dong@intel.com>,
	"Dugger, Donald D" <donald.d.dugger@intel.com>,
	"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>,
	"dietmar.hahn@ts.fujitsu.com" <dietmar.hahn@ts.fujitsu.com>,
	"JBeulich@suse.com" <JBeulich@suse.com>,
	"suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com>
Subject: Re: [PATCH v5 RESEND 04/17] intel/VPMU: Clean up Intel VPMU code
Date: Mon, 28 Apr 2014 10:00:00 -0400	[thread overview]
Message-ID: <535E5EE0.8050804@oracle.com> (raw)
In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D125E517F5@SHSMSX101.ccr.corp.intel.com>

On 04/26/2014 04:20 AM, Tian, Kevin wrote:
>> From: Boris Ostrovsky [mailto:boris.ostrovsky@oracle.com]
>> Sent: Wednesday, April 23, 2014 8:50 PM
>>
>> Remove struct pmumsr and core2_pmu_enable. Replace static MSR structures
>> with
>> fields in core2_vpmu_context.
>>
>> Call core2_get_pmc_count() once, during initialization.
>>
>> Properly clean up when core2_vpmu_alloc_resource() fails and add routines
>> to remove MSRs from VMCS.
>>
>>
>> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
> it's a good cleanup in general. ack with two small comments later.
>
> Acked-by: Kevin Tian <kevin.tian@intel.com>
>
>
>> ---
>>   xen/arch/x86/hvm/vmx/vmcs.c              |  55 ++++++
>>   xen/arch/x86/hvm/vmx/vpmu_core2.c        | 310
>> ++++++++++++++-----------------
>>   xen/include/asm-x86/hvm/vmx/vmcs.h       |   2 +
>>   xen/include/asm-x86/hvm/vmx/vpmu_core2.h |  19 --
>>   4 files changed, 199 insertions(+), 187 deletions(-)
>>
>> diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
>> index 44f33cb..5f86b17 100644
>> --- a/xen/arch/x86/hvm/vmx/vmcs.c
>> +++ b/xen/arch/x86/hvm/vmx/vmcs.c
>> @@ -1205,6 +1205,34 @@ int vmx_add_guest_msr(u32 msr)
>>       return 0;
>>   }
>>
>> +void vmx_rm_guest_msr(u32 msr)
>> +{
>> +    struct vcpu *curr = current;
>> +    unsigned int idx, msr_count = curr->arch.hvm_vmx.msr_count;
>> +    struct vmx_msr_entry *msr_area = curr->arch.hvm_vmx.msr_area;
>> +
>> +    if ( msr_area == NULL )
>> +        return;
>> +
>> +    for ( idx = 0; idx < msr_count; idx++ )
>> +        if ( msr_area[idx].index == msr )
>> +            break;
>> +
>> +    if ( idx == msr_count )
>> +        return;
>> +
>> +    for ( ; idx < msr_count - 1; idx++ )
>> +    {
>> +        msr_area[idx].index = msr_area[idx + 1].index;
>> +        msr_area[idx].data = msr_area[idx + 1].data;
>> +    }
>> +    msr_area[msr_count - 1].index = 0;
>> +
>> +    curr->arch.hvm_vmx.msr_count = --msr_count;
>> +    __vmwrite(VM_EXIT_MSR_STORE_COUNT, msr_count);
>> +    __vmwrite(VM_ENTRY_MSR_LOAD_COUNT, msr_count);
>> +}
>> +
>>   int vmx_add_host_load_msr(u32 msr)
>>   {
>>       struct vcpu *curr = current;
>> @@ -1235,6 +1263,33 @@ int vmx_add_host_load_msr(u32 msr)
>>       return 0;
>>   }
>>
>> +void vmx_rm_host_load_msr(u32 msr)
>> +{
>> +    struct vcpu *curr = current;
>> +    unsigned int idx,  msr_count = curr->arch.hvm_vmx.host_msr_count;
>> +    struct vmx_msr_entry *msr_area =
>> curr->arch.hvm_vmx.host_msr_area;
>> +
>> +    if ( msr_area == NULL )
>> +        return;
>> +
>> +    for ( idx = 0; idx < msr_count; idx++ )
>> +        if ( msr_area[idx].index == msr )
>> +            break;
>> +
>> +    if ( idx == msr_count )
>> +        return;
>> +
>> +    for ( ; idx < msr_count - 1; idx++ )
>> +    {
>> +        msr_area[idx].index = msr_area[idx + 1].index;
>> +        msr_area[idx].data = msr_area[idx + 1].data;
>> +    }
>> +    msr_area[msr_count - 1].index = 0;
>> +
>> +    curr->arch.hvm_vmx.host_msr_count = --msr_count;
>> +    __vmwrite(VM_EXIT_MSR_LOAD_COUNT, msr_count);
>> +}
>> +
> suggest to combine common code in above two 'rm' functions. You can pass in
> a msr_area pointer/count , and only last several lines actually differ.

I then should see if I can merge vmx_add_guest_msr/vmx_add_host_load_msr 
as well since they have similarities too.

>
>>   void vmx_set_eoi_exit_bitmap(struct vcpu *v, u8 vector)
>>   {
>>       if ( !test_and_set_bit(vector, v->arch.hvm_vmx.eoi_exit_bitmap) )
>> diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c
>> b/xen/arch/x86/hvm/vmx/vpmu_core2.c
>> index 1e32ff3..513eca4 100644
>> --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
>> +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
>> @@ -69,6 +69,26 @@
>>   static bool_t __read_mostly full_width_write;
>>
>>   /*
>> + * MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed
>> + * counters. 4 bits for every counter.
>> + */
>> +#define FIXED_CTR_CTRL_BITS 4
>> +#define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1)
>> +
>> +#define VPMU_CORE2_MAX_FIXED_PMCS     4
>> +struct core2_vpmu_context {
>> +    u64 fixed_ctrl;
>> +    u64 ds_area;
>> +    u64 pebs_enable;
> just stay 'pebs' to be consistent.

The name is was chosen to reflect the MSR name (MSR_IA32_PEBS_ENABLE).

-boris

>
>> +    u64 global_ovf_status;
>> +    u64 fix_counters[VPMU_CORE2_MAX_FIXED_PMCS];
>> +    struct arch_msr_pair arch_msr_pair[1];
>> +};
>> +

  reply	other threads:[~2014-04-28 14:00 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-23 12:50 [PATCH v5 RESEND 00/17] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2014-04-23 12:50 ` [PATCH v5 RESEND 01/17] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2014-04-23 12:50 ` [PATCH v5 RESEND 02/17] VPMU: Mark context LOADED before registers are loaded Boris Ostrovsky
2014-04-26  8:20   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 03/17] x86/VPMU: Minor VPMU cleanup Boris Ostrovsky
2014-04-26  8:20   ` Tian, Kevin
2014-04-28 13:52     ` Boris Ostrovsky
2014-04-23 12:50 ` [PATCH v5 RESEND 04/17] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
2014-04-26  8:20   ` Tian, Kevin
2014-04-28 14:00     ` Boris Ostrovsky [this message]
2014-04-23 12:50 ` [PATCH v5 RESEND 05/17] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
2014-04-26  8:20   ` Tian, Kevin
2014-04-28 14:05     ` Boris Ostrovsky
2014-04-23 12:50 ` [PATCH v5 RESEND 06/17] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero Boris Ostrovsky
2014-04-26  8:20   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 07/17] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2014-04-26  8:21   ` Tian, Kevin
2014-04-28  9:03     ` Jan Beulich
2014-04-28  9:09       ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 08/17] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2014-04-26  8:21   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 09/17] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2014-04-26  8:21   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 10/17] x86/VPMU: Initialize PMU for PV guests Boris Ostrovsky
2014-04-26  8:21   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 11/17] x86/VPMU: Add support for PMU register handling on " Boris Ostrovsky
2014-04-26  8:26   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 12/17] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
2014-04-26  8:33   ` Tian, Kevin
2014-04-28 14:15     ` Boris Ostrovsky
2014-04-23 12:50 ` [PATCH v5 RESEND 13/17] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2014-04-26  8:39   ` Tian, Kevin
2014-04-28 14:23     ` Boris Ostrovsky
2014-04-23 12:50 ` [PATCH v5 RESEND 14/17] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2014-04-26  8:40   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 15/17] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
2014-04-26  8:48   ` Tian, Kevin
2014-04-28 17:06     ` Boris Ostrovsky
2014-04-23 12:50 ` [PATCH v5 RESEND 16/17] x86/VPMU: Suport for PVH guests Boris Ostrovsky
2014-04-26  8:50   ` Tian, Kevin
2014-04-23 12:50 ` [PATCH v5 RESEND 17/17] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
2014-04-26  8:52   ` Tian, Kevin
2014-04-24  9:22 ` [PATCH v5 RESEND 00/17] x86/PMU: Xen PMU PV(H) support Tian, Kevin
2014-04-26  8:55 ` Tian, Kevin

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