[PATCH v9 0/3] Expose HW APIC virtualization support to HVM guests

[PATCH v9 0/3] Expose HW APIC virtualization support to HVM guests

[Boris Ostrovsky]

Version 9:
* Set max number of hypervisor leaves to 2 if user specifies fewer than 2.

Version 8:
* Changed minimum largest hypervisor leaf from 1 to 2 (hvmloader.c:init_hypercalls()
  doen't like max leaf 1)
* Added 'maxhvleaf' string as alias for 0x400000XX_EAX. (No alias for Viridian
  guests though)
* Docs updates
* Changed conditions for setting XEN_HVM_CPUID_X2APIC_VIRT bit based on 
  vmx_vlapic_msr_changed() behavior. (Yang is still not convinced that 2 bits
  are needed but is OK to keep them if others agree)

(Jan, I dropped your Reviewed-by for the first patch because of the first three
bullets)

Version 7:
* Enforce user-specified number of leaves between 1 and XEN_CPUID_MAX_NUM_LEAVES
* Merge Solaris patch reversal into the first patch

Version 6:
* Drop generic support for changing hypervisor leaves, only allow modifying max
  number of leaves, ignore all other bit change requests.

Version 5:
* Remember to deal with Viridian leaves in xc_cpuid_constrain()

Version 4:
* asm changes per Jan's suggestions
* Don't pass leaf index number to handlers, check for sub_idx==0
* Added (possibly somewhat overwrought) interface to constrain user-requested
  CPUID to what is allowed (specifically, for leaf 0x40000000 only EAX[7:0]
  can be ovverwritten).

Version 3:
* Removed sysctl for querying hypervisor leaf from libxc, replaced it with
  prefixed CPUID instruction
* Limited ability change hypervisor leaves to 0x40000000
* Fixed IS_HYPERVISOR_LEAF macro

Version 2:
* Added ability to specify hypervisor CPUID leaves in config file (this requires
  new sysctl)
* Use 2 bits to indicate what is supported --- one for APIC memory access and the
  other for x2APIC. Still not sure whether virtual interrupt delivery should be
  exposed as well.



HVM guests running on HW that supports HW APIC virtualization features
(APIC-register virtualization, virtual interrupt delivery, etc) may
want to use APIC instead of hvm_pirqs. Since we are not guaranteed to
have these features on VMX (for example, there is a boot option to
turn it off) and there is no such support on SVM we need to make the
guest aware that its APIC accesses may not be so bad.

CPUID seems to be a good way to provide this info to the guest.

Having a guest switch to APIC shows fairly good impact on number of
VMEXITs. For example, with a pass-through NIC, netperf sees almost
half as many. Here are results for 'xentrace -e 0x00083fff -c 2 -D -T 2'

(The guest here essentially turned off XENFEAT_hvm_pirqs but we may
want to use APIC for MSI interrupts only and leave pirqs for gsi).


[root@ovs105 virt]#  cat orig  |xentrace_format  ~/xen/tools/xentrace/formats | awk  '{print $5}' | sort  | uniq -c
     94 cpu_change
  13944 HLT
  26341 INJ_VIRQ
  12054 INTR
  30784 INTR_WINDOW
  10126 TRAP
 124783 VMENTRY
 124782 VMEXIT
  59217 VMMCALL
     35 wrap_buffer
 
 
[root@ovs105 virt]#  cat apicv  |xentrace_format  ~/xen/tools/xentrace/formats | awk  '{print $5}' | sort  | uniq -c
     49 cpu_change
  16157 HLT
     31 INJ_VIRQ
  10652 INTR
     38 INTR_WINDOW
     10 NPF
  10286 TRAP
  71269 VMENTRY
  71269 VMEXIT
  34129 VMMCALL
     15 wrap_buffer

The difference is even larger when the guest is busy.

These results are in line with what has been reported for KVM. For example
http://events.linuxfoundation.org/sites/events/files/cojp13_natapov.pdf
http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf

I am also not sure whether (cpu_has_vmx_apic_reg_virt &
cpu_has_vmx_virtualize_x2apic_mode) is sufficient to declare full HW
APIC support to a guest. The tests show ~95K VMEXITs when virtual
interrupt delivery and posted interrupts are turned off so there
appears to still be some benefit. I suppose we can use another CPUID
bit for these two (although I am not particularly eager to do this).


Boris Ostrovsky (3):
  xen/libxc: Allow changing max number of hypervisor cpuid leaves
  x86/hvm: Add HVM-specific hypervisor CPUID leaf
  x86/hvm: Indicate avaliability of HW support of APIC virtualization
    to HVM guests

 docs/man/xl.cfg.pod.5               |    8 ++++++--
 tools/libxc/xc_cpuid_x86.c          |   11 +++++++++++
 tools/libxl/libxl_cpuid.c           |    1 +
 xen/arch/x86/hvm/hvm.c              |    9 +++++++++
 xen/arch/x86/hvm/vmx/vmx.c          |   21 +++++++++++++++++++++
 xen/arch/x86/traps.c                |   20 ++++++++++++++------
 xen/include/asm-x86/hvm/hvm.h       |    7 +++++++
 xen/include/public/arch-x86/cpuid.h |   11 +++++++++++
 8 files changed, 80 insertions(+), 8 deletions(-)

[PATCH v9 1/3] xen/libxc: Allow changing max number of hypervisor cpuid leaves

[Boris Ostrovsky]

Add support for changing max number of hypervisor leaves from configuration
file.

This number can be specified using xl's standard 'cpuid' option. Only lowest
8 bits of leaf's 0x4000xx00 eax register are processed, all others are ignored.

The changes allow us to revert commit 80ecb40362365ba77e68fc609de8bd3b7208ae19
which is most likely no longer needed now anyway (Solaris bug that it addressed
has been fixed and backported to earlier releases) but leave possibility of
running unpatched version of Solaris by forcing number of leaves to 2 in the
configuration file.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
 docs/man/xl.cfg.pod.5               |    8 ++++++--
 tools/libxc/xc_cpuid_x86.c          |   11 +++++++++++
 tools/libxl/libxl_cpuid.c           |    1 +
 xen/arch/x86/traps.c                |   18 +++++++++++-------
 xen/include/public/arch-x86/cpuid.h |    2 ++
 5 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/docs/man/xl.cfg.pod.5 b/docs/man/xl.cfg.pod.5
index a6663b9..3c557c8 100644
--- a/docs/man/xl.cfg.pod.5
+++ b/docs/man/xl.cfg.pod.5
@@ -873,9 +873,13 @@ Possible values for a single feature bit:
   'k' -> pass through the host bit value
   's' -> as 'k' but preserve across save/restore and migration (not implemented)
 
+Note: when specifying B<cpuid> for hypervisor leaves (0x4000xxxx major group)
+only the lowest 8 bits of leaf's 0x4000xx00 EAX register are processed, the rest
+are ignored (these 8 bits signify maximum number of hypervisor leaves).
+
 List of keys taking a value:
-apicidsize brandid clflush family localapicid maxleaf model nc proccount procpkg
-stepping
+apicidsize brandid clflush family localapicid maxleaf maxhvleaf model nc
+proccount procpkg stepping
 
 List of keys taking a character:
 3dnow 3dnowext 3dnowprefetch abm acpi aes altmovcr8 apic avx clfsh cmov
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 9264039..f0aa31d 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -560,6 +560,17 @@ static int xc_cpuid_policy(
 {
     xc_dominfo_t        info;
 
+    /*
+     * For hypervisor leaves (0x4000XXXX) only 0x4000xx00.EAX[7:0] bits (max
+     * number of leaves) can be set by user. Hypervisor will enforce this so
+     * all other bits are don't-care and we can set them to zero.
+     */
+    if ( (input[0] & 0xffff0000) == 0x40000000 )
+    {
+        regs[0] = regs[1] = regs[2] = regs[3] = 0;
+        return 0;
+    }
+
     if ( xc_domain_getinfo(xch, domid, 1, &info) == 0 )
         return -EINVAL;
 
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index dd21b78..d1ea50d 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -187,6 +187,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
         {"svm_vmcbclean",0x8000000a, NA, CPUID_REG_EDX,  5,  1},
         {"svm_decode",   0x8000000a, NA, CPUID_REG_EDX,  7,  1},
         {"svm_pausefilt",0x8000000a, NA, CPUID_REG_EDX, 10,  1},
+        {"maxhvleaf",    0x40000000, NA, CPUID_REG_EAX,  0,  8},
 
         {NULL, 0, NA, CPUID_REG_INV, 0, 0}
     };
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index b7303d7..48d722d 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -677,15 +677,19 @@ int cpuid_hypervisor_leaves( uint32_t idx, uint32_t sub_idx,
     struct domain *d = current->domain;
     /* Optionally shift out of the way of Viridian architectural leaves. */
     uint32_t base = is_viridian_domain(d) ? 0x40000100 : 0x40000000;
-    uint32_t limit;
+    uint32_t limit, dummy;
 
     idx -= base;
-
-    /*
-     * Some Solaris PV drivers fail if max > base + 2. Help them out by
-     * hiding the PVRDTSCP leaf if PVRDTSCP is disabled.
-     */
-    limit = (d->arch.tsc_mode < TSC_MODE_PVRDTSCP) ? 2 : 3;
+    if ( idx > XEN_CPUID_MAX_NUM_LEAVES )
+        return 0; /* Avoid unnecessary pass through domain_cpuid() */
+
+    /* Number of leaves may be user-specified */
+    domain_cpuid(d, base, 0, &limit, &dummy, &dummy, &dummy);
+    limit &= 0xff;
+    if ( limit < 2 )
+        limit = 2;
+    else if ( limit > XEN_CPUID_MAX_NUM_LEAVES )
+        limit = XEN_CPUID_MAX_NUM_LEAVES;
 
     if ( idx > limit ) 
         return 0;
diff --git a/xen/include/public/arch-x86/cpuid.h b/xen/include/public/arch-x86/cpuid.h
index d9bd627..19fc9dd 100644
--- a/xen/include/public/arch-x86/cpuid.h
+++ b/xen/include/public/arch-x86/cpuid.h
@@ -65,4 +65,6 @@
 #define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
 #define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD  (1u<<0)
 
+#define XEN_CPUID_MAX_NUM_LEAVES 3
+
 #endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
-- 
1.7.1

Re: [PATCH v9 1/3] xen/libxc: Allow changing max number of hypervisor cpuid leaves

[Ian Campbell]

On Tue, 2014-04-22 at 15:17 -0400, Boris Ostrovsky wrote:
> Add support for changing max number of hypervisor leaves from configuration
> file.
> 
> This number can be specified using xl's standard 'cpuid' option. Only lowest
> 8 bits of leaf's 0x4000xx00 eax register are processed, all others are ignored.
> 
> The changes allow us to revert commit 80ecb40362365ba77e68fc609de8bd3b7208ae19
> which is most likely no longer needed now anyway (Solaris bug that it addressed
> has been fixed and backported to earlier releases) but leave possibility of
> running unpatched version of Solaris by forcing number of leaves to 2 in the
> configuration file.
> 
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

I'm happy with this if Jan is:
        Acked-by: Ian Campbell <ian.campbell@citrix.com>
        
I assume Jan will apply along with the h/v side.

Re: [PATCH v9 1/3] xen/libxc: Allow changing max number of hypervisor cpuid leaves

[Jan Beulich]

>>> On 23.04.14 at 10:42, <Ian.Campbell@citrix.com> wrote:
> On Tue, 2014-04-22 at 15:17 -0400, Boris Ostrovsky wrote:
>> Add support for changing max number of hypervisor leaves from configuration
>> file.
>> 
>> This number can be specified using xl's standard 'cpuid' option. Only lowest
>> 8 bits of leaf's 0x4000xx00 eax register are processed, all others are 
> ignored.
>> 
>> The changes allow us to revert commit 
> 80ecb40362365ba77e68fc609de8bd3b7208ae19
>> which is most likely no longer needed now anyway (Solaris bug that it 
> addressed
>> has been fixed and backported to earlier releases) but leave possibility of
>> running unpatched version of Solaris by forcing number of leaves to 2 in the
>> configuration file.
>> 
>> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
> 
> I'm happy with this if Jan is:
>         Acked-by: Ian Campbell <ian.campbell@citrix.com>

I am (minus the stray printk() in patch 3 that I just commented on).

> I assume Jan will apply along with the h/v side.

I'll definitely want a VMX maintainer's ack (or at least Yang's consent)
on patch 3 before applying the whole series (the first two patches
alone don't make that much sense).

Jan

Re: [PATCH v9 1/3] xen/libxc: Allow changing max number of hypervisor cpuid leaves

[Zhang, Yang Z]

Jan Beulich wrote on 2014-04-23:
>>>> On 23.04.14 at 10:42, <Ian.Campbell@citrix.com> wrote:
>> On Tue, 2014-04-22 at 15:17 -0400, Boris Ostrovsky wrote:
>>> Add support for changing max number of hypervisor leaves from
>>> configuration file.
>>> 
>>> This number can be specified using xl's standard 'cpuid' option. Only
>>> lowest 8 bits of leaf's 0x4000xx00 eax register are processed, all
>>> others are ignored.
>>> 
>>> The changes allow us to revert commit
>>> 80ecb40362365ba77e68fc609de8bd3b7208ae19 which is most likely no
>>> longer needed now anyway (Solaris bug that it addressed has been fixed
>>> and backported to earlier releases) but leave possibility of running
>>> unpatched version of Solaris by forcing number of leaves to 2 in the
>>> configuration file.
>>> 
>>> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
>> 
>> I'm happy with this if Jan is:
>>         Acked-by: Ian Campbell <ian.campbell@citrix.com>
> 
> I am (minus the stray printk() in patch 3 that I just commented on).
> 
>> I assume Jan will apply along with the h/v side.
> 
> I'll definitely want a VMX maintainer's ack (or at least Yang's
> consent) on patch
> 3 before applying the whole series (the first two patches alone don't
> make that much sense).

I have discussed with Boris before (offlist) and I don't think it is necessary to expose two bits. Per my understanding, only one bit to indicate whether APICv is enabled should be enough. The reason is that all hardwires that support APICv must also support virtualized x2apic(Intel SDM doesn't say it explicitly, but I get confirmed from hardware guys). And in current Xen's implementation, it will enable APICv and virtualize_x2apic unconditionally if hardware support them and not disabled by user. So based on current xen's implementation, APICv is enabled means virtulized x2apic is enabled, vice versa. That's the reason why I think one bit is enough.
But if you guys think two bits also is acceptable, I am ok.

> 
> Jan


Best regards,
Yang

Re: [PATCH v9 1/3] xen/libxc: Allow changing max number of hypervisor cpuid leaves

[Boris Ostrovsky]

On 04/23/2014 08:36 PM, Zhang, Yang Z wrote:
> Jan Beulich wrote on 2014-04-23:
>> I'll definitely want a VMX maintainer's ack (or at least Yang's 
>> consent) on patch 3 before applying the whole series (the first two 
>> patches alone don't make that much sense). 
> I have discussed with Boris before (offlist) and I don't think it is necessary to expose two bits. Per my understanding, only one bit to indicate whether APICv is enabled should be enough. The reason is that all hardwires that support APICv must also support virtualized x2apic(Intel SDM doesn't say it explicitly, but I get confirmed from hardware guys). And in current Xen's implementation, it will enable APICv and virtualize_x2apic unconditionally if hardware support them and not disabled by user. So based on current xen's implementation, APICv is enabled means virtulized x2apic is enabled, vice versa. That's the reason why I think one bit is enough.
> But if you guys think two bits also is acceptable, I am ok.


Jan, how do you want to proceed? Although I didn't realize that x2apic 
virtualization is guaranteed for APICv-enabled silicon I still prefer to 
keep separate bits for x2apic vs plain APIC for guests that can only use 
the latter.

(I know that I need to resend this in any case with stray printk removed)

-boris

Re: [PATCH v9 1/3] xen/libxc: Allow changing max number of hypervisor cpuid leaves

[Jan Beulich]

>>> On 06.05.14 at 17:23, <boris.ostrovsky@oracle.com> wrote:
> On 04/23/2014 08:36 PM, Zhang, Yang Z wrote:
>> Jan Beulich wrote on 2014-04-23:
>>> I'll definitely want a VMX maintainer's ack (or at least Yang's 
>>> consent) on patch 3 before applying the whole series (the first two 
>>> patches alone don't make that much sense). 
>> I have discussed with Boris before (offlist) and I don't think it is 
> necessary to expose two bits. Per my understanding, only one bit to indicate 
> whether APICv is enabled should be enough. The reason is that all hardwires 
> that support APICv must also support virtualized x2apic(Intel SDM doesn't say 
> it explicitly, but I get confirmed from hardware guys). And in current Xen's 
> implementation, it will enable APICv and virtualize_x2apic unconditionally if 
> hardware support them and not disabled by user. So based on current xen's 
> implementation, APICv is enabled means virtulized x2apic is enabled, vice 
> versa. That's the reason why I think one bit is enough.
>> But if you guys think two bits also is acceptable, I am ok.
> 
> 
> Jan, how do you want to proceed? Although I didn't realize that x2apic 
> virtualization is guaranteed for APICv-enabled silicon I still prefer to 
> keep separate bits for x2apic vs plain APIC for guests that can only use 
> the latter.
> 
> (I know that I need to resend this in any case with stray printk removed)

I already committed the patches a couple of days ago (with that
printk() removed).

Jan

[PATCH v9 2/3] x86/hvm: Add HVM-specific hypervisor CPUID leaf

[Boris Ostrovsky]

CPUID leaf 0x40000004 is for HVM-specific features.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-off-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/hvm/hvm.c              |    9 +++++++++
 xen/arch/x86/traps.c                |    4 ++++
 xen/include/asm-x86/hvm/hvm.h       |    7 +++++++
 xen/include/public/arch-x86/cpuid.h |    7 ++++++-
 4 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index ae7a645..16b968c 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -2983,6 +2983,15 @@ unsigned long copy_from_user_hvm(void *to, const void *from, unsigned len)
     return rc ? len : 0; /* fake a copy_from_user() return code */
 }
 
+void hvm_hypervisor_cpuid_leaf(uint32_t sub_idx,
+                               uint32_t *eax, uint32_t *ebx,
+                               uint32_t *ecx, uint32_t *edx)
+{
+    *eax = *ebx = *ecx = *edx = 0;
+    if ( hvm_funcs.hypervisor_cpuid_leaf )
+        hvm_funcs.hypervisor_cpuid_leaf(sub_idx, eax, ebx, ecx, edx);
+}
+
 void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
                                    unsigned int *ecx, unsigned int *edx)
 {
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 48d722d..dfced11 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -726,6 +726,10 @@ int cpuid_hypervisor_leaves( uint32_t idx, uint32_t sub_idx,
         cpuid_time_leaf( sub_idx, eax, ebx, ecx, edx );
         break;
 
+    case 4:
+        hvm_hypervisor_cpuid_leaf(sub_idx, eax, ebx, ecx, edx);
+        break;
+
     default:
         BUG();
     }
diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h
index dcc3483..a030ea4 100644
--- a/xen/include/asm-x86/hvm/hvm.h
+++ b/xen/include/asm-x86/hvm/hvm.h
@@ -200,6 +200,10 @@ struct hvm_function_table {
                                 paddr_t *L1_gpa, unsigned int *page_order,
                                 uint8_t *p2m_acc, bool_t access_r,
                                 bool_t access_w, bool_t access_x);
+
+    void (*hypervisor_cpuid_leaf)(uint32_t sub_idx,
+                                  uint32_t *eax, uint32_t *ebx,
+                                  uint32_t *ecx, uint32_t *edx);
 };
 
 extern struct hvm_function_table hvm_funcs;
@@ -336,6 +340,9 @@ static inline unsigned long hvm_get_shadow_gs_base(struct vcpu *v)
 #define is_viridian_domain(_d)                                             \
  (is_hvm_domain(_d) && ((_d)->arch.hvm_domain.params[HVM_PARAM_VIRIDIAN]))
 
+void hvm_hypervisor_cpuid_leaf(uint32_t sub_idx,
+                               uint32_t *eax, uint32_t *ebx,
+                               uint32_t *ecx, uint32_t *edx);
 void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
                                    unsigned int *ecx, unsigned int *edx);
 void hvm_migrate_timers(struct vcpu *v);
diff --git a/xen/include/public/arch-x86/cpuid.h b/xen/include/public/arch-x86/cpuid.h
index 19fc9dd..fff972a 100644
--- a/xen/include/public/arch-x86/cpuid.h
+++ b/xen/include/public/arch-x86/cpuid.h
@@ -65,6 +65,11 @@
 #define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
 #define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD  (1u<<0)
 
-#define XEN_CPUID_MAX_NUM_LEAVES 3
+/*
+ * Leaf 5 (0x40000004)
+ * HVM-specific features
+ */
+
+#define XEN_CPUID_MAX_NUM_LEAVES 4
 
 #endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
-- 
1.7.1

[PATCH v9 3/3] x86/hvm: Indicate avaliability of HW support of APIC virtualization to HVM guests

[Boris Ostrovsky]

Set bits in hypervisor CPUID leaf indicating that HW provides (and the
hypervisor enables) HW support for APIC and x2APIC virtualization.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
 xen/arch/x86/hvm/vmx/vmx.c          |   21 +++++++++++++++++++++
 xen/include/public/arch-x86/cpuid.h |    4 ++++
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 180cf6c..9fbd2f9 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -57,6 +57,7 @@
 #include <asm/apic.h>
 #include <asm/hvm/nestedhvm.h>
 #include <asm/event.h>
+#include <public/arch-x86/cpuid.h>
 
 enum handler_return { HNDL_done, HNDL_unhandled, HNDL_exception_raised };
 
@@ -1651,6 +1652,25 @@ static void vmx_handle_eoi(u8 vector)
     __vmwrite(GUEST_INTR_STATUS, status);
 }
 
+void vmx_hypervisor_cpuid_leaf(uint32_t sub_idx,
+                               uint32_t *eax, uint32_t *ebx,
+                               uint32_t *ecx, uint32_t *edx)
+{
+    if ( sub_idx != 0 )
+        return;
+printk("cpu_has_vmx_apic_reg_virt=0x%x cpu_has_vmx_virtualize_x2apic_mode=0x%x cpu_has_vmx_apic_reg_virt=0x%x cpu_has_vmx_virtual_intr_delivery=0x%x\n", cpu_has_vmx_apic_reg_virt, cpu_has_vmx_virtualize_x2apic_mode, cpu_has_vmx_apic_reg_virt, cpu_has_vmx_virtual_intr_delivery);
+    if ( cpu_has_vmx_apic_reg_virt )
+        *eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
+    /*
+     * We want to claim that x2APIC is virtualized if APIC MSR accesses are
+     * not intercepted. When all three of these are true both rdmsr and wrmsr
+     * in the guest will run without VMEXITs (see vmx_vlapic_msr_changed()).
+     */
+    if ( cpu_has_vmx_virtualize_x2apic_mode && cpu_has_vmx_apic_reg_virt &&
+         cpu_has_vmx_virtual_intr_delivery)
+        *eax |= XEN_HVM_CPUID_X2APIC_VIRT;
+}
+
 static struct hvm_function_table __initdata vmx_function_table = {
     .name                 = "VMX",
     .cpu_up_prepare       = vmx_cpu_up_prepare,
@@ -1708,6 +1728,7 @@ static struct hvm_function_table __initdata vmx_function_table = {
     .sync_pir_to_irr      = vmx_sync_pir_to_irr,
     .handle_eoi           = vmx_handle_eoi,
     .nhvm_hap_walk_L1_p2m = nvmx_hap_walk_L1_p2m,
+    .hypervisor_cpuid_leaf= vmx_hypervisor_cpuid_leaf,
 };
 
 const struct hvm_function_table * __init start_vmx(void)
diff --git a/xen/include/public/arch-x86/cpuid.h b/xen/include/public/arch-x86/cpuid.h
index fff972a..7135d54 100644
--- a/xen/include/public/arch-x86/cpuid.h
+++ b/xen/include/public/arch-x86/cpuid.h
@@ -70,6 +70,10 @@
  * HVM-specific features
  */
 
+/* EAX Features */
+#define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */
+#define XEN_HVM_CPUID_X2APIC_VIRT      (1u << 1) /* Virtualized x2APIC accesses */
+
 #define XEN_CPUID_MAX_NUM_LEAVES 4
 
 #endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
-- 
1.7.1

Re: [PATCH v9 3/3] x86/hvm: Indicate avaliability of HW support of APIC virtualization to HVM guests

[Jan Beulich]

>>> On 22.04.14 at 21:17, <boris.ostrovsky@oracle.com> wrote:
> +void vmx_hypervisor_cpuid_leaf(uint32_t sub_idx,
> +                               uint32_t *eax, uint32_t *ebx,
> +                               uint32_t *ecx, uint32_t *edx)
> +{
> +    if ( sub_idx != 0 )
> +        return;
> +printk("cpu_has_vmx_apic_reg_virt=0x%x 
> cpu_has_vmx_virtualize_x2apic_mode=0x%x cpu_has_vmx_apic_reg_virt=0x%x 
> cpu_has_vmx_virtual_intr_delivery=0x%x\n", cpu_has_vmx_apic_reg_virt, 
> cpu_has_vmx_virtualize_x2apic_mode, cpu_has_vmx_apic_reg_virt, 
> cpu_has_vmx_virtual_intr_delivery);

Urgh?!

Jan

Re: [PATCH v9 3/3] x86/hvm: Indicate avaliability of HW support of APIC virtualization to HVM guests

[Boris Ostrovsky]

On 04/23/2014 05:44 AM, Jan Beulich wrote:
>>>> On 22.04.14 at 21:17, <boris.ostrovsky@oracle.com> wrote:
>> +void vmx_hypervisor_cpuid_leaf(uint32_t sub_idx,
>> +                               uint32_t *eax, uint32_t *ebx,
>> +                               uint32_t *ecx, uint32_t *edx)
>> +{
>> +    if ( sub_idx != 0 )
>> +        return;
>> +printk("cpu_has_vmx_apic_reg_virt=0x%x
>> cpu_has_vmx_virtualize_x2apic_mode=0x%x cpu_has_vmx_apic_reg_virt=0x%x
>> cpu_has_vmx_virtual_intr_delivery=0x%x\n", cpu_has_vmx_apic_reg_virt,
>> cpu_has_vmx_virtualize_x2apic_mode, cpu_has_vmx_apic_reg_virt,
>> cpu_has_vmx_virtual_intr_delivery);
> Urgh?!
>
> Jan
>

<blush>

I'll fix this after Intel folks comment on this patch.


-boris