From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v5 2/6] xen/arm: IRQ: Store IRQ type in arch_irq_desc Date: Mon, 12 May 2014 13:34:05 +0100 Message-ID: <5370BFBD.2010308@linaro.org> References: <1399045930-17364-1-git-send-email-julien.grall@linaro.org> <1399045930-17364-3-git-send-email-julien.grall@linaro.org> <1399543402.9513.28.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WjpQn-0003ps-0k for xen-devel@lists.xenproject.org; Mon, 12 May 2014 12:34:09 +0000 Received: by mail-ee0-f45.google.com with SMTP id d49so4549164eek.18 for ; Mon, 12 May 2014 05:34:07 -0700 (PDT) In-Reply-To: <1399543402.9513.28.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: xen-devel@lists.xenproject.org, tim@xen.org, stefano.stabellini@citrix.com List-Id: xen-devel@lists.xenproject.org Hi Ian, On 05/08/2014 11:03 AM, Ian Campbell wrote: > On Fri, 2014-05-02 at 16:52 +0100, Julien Grall wrote: >> For now, ARM uses different IRQ functions to setup an interrupt handler. This >> is a bit annoying for common driver because we have to add idefery when >> an IRQ is setup (see ns16550_init_postirq for an example). >> >> To avoid to completely fork the IRQ management code, we can introduce a field >> to store the IRQ type (e.g level/edge ...). >> >> This patch also adds platform_get_irq which will retrieve the IRQ from the >> device tree and setup correctly the IRQ type. >> >> In order to use this solution, we have to move init_IRQ earlier for the boot >> CPU. It's fine because the code only depends on percpu. >> >> Signed-off-by: Julien Grall > > Looks good. But based on the comments raised previously I am wondering > if > static int ppi_types[NR_PPIS] > which is set on configuration of such an interrupt and propagated to the > cpu local copy when a CPU comes up? > > Apart from avoiding the slightly odd per_cpu(0) (even if hidden behind a > macro) it also means that there is less need to be concerned about which > processor ends up initialising an interrupt, which would simplify some > stuff around irq_set_type and platform_get_irq (essentially you could > then sanity check the change against ppi_types and then propagate to all > online cpus without further checks). > > Thoughts? It looks good to me. I will give a try with this solution. -- Julien Grall