From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v8 09/13] xen/arm: second irq injection while the first irq is still inflight Date: Thu, 22 May 2014 16:48:55 +0100 Message-ID: <537E1C67.2020302@linaro.org> References: <1400761950-25035-9-git-send-email-stefano.stabellini@eu.citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1400761950-25035-9-git-send-email-stefano.stabellini@eu.citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini , xen-devel@lists.xensource.com Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com List-Id: xen-devel@lists.xenproject.org On 22/05/14 13:32, Stefano Stabellini wrote: > Set GICH_LR_PENDING in the corresponding GICH_LR to inject a second irq > while the first one is still active. > If the first irq is already pending (not active), clear > GIC_IRQ_GUEST_QUEUED because the guest doesn't need a second > notification.If the irq has already been EOI'ed then just clear the > GICH_LR right away and move the interrupt to lr_pending so that it is > going to be reinjected by gic_restore_pending_irqs on return to guest. > > If the target cpu is not the current cpu, then set GIC_IRQ_GUEST_QUEUED > and send an SGI. The target cpu is going to be interrupted and call > gic_clear_lrs, that is going to take the same actions. > > Do not call vgic_vcpu_inject_irq from gic_inject if > evtchn_upcall_pending is set. If we remove that call, we don't need to > special case evtchn_irq in vgic_vcpu_inject_irq anymore. > We need to force the first injection of evtchn_irq (call > gic_vcpu_inject_irq) from vgic_enable_irqs because evtchn_upcall_pending > is already set by common code on vcpu creation. If you only need it for the first time. Why can't you call vgic_inject_irq with the IRQ evtchn when the VCPU is turn on? This would remove every hack with this IRQ in the GIC code. > --- > xen/arch/arm/gic.c | 48 +++++++++++++++++++++++++++++++++++++-------- > xen/arch/arm/vgic.c | 11 +++++++---- > xen/include/asm-arm/gic.h | 1 + > 3 files changed, 48 insertions(+), 12 deletions(-) > > diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c > index 89d7025..a6fe566 100644 > --- a/xen/arch/arm/gic.c > +++ b/xen/arch/arm/gic.c > @@ -66,6 +66,8 @@ static DEFINE_PER_CPU(u8, gic_cpu_id); > /* Maximum cpu interface per GIC */ > #define NR_GIC_CPU_IF 8 > > +#undef GIC_DEBUG >+ Did you intend to keep the debug in the final patch? Regards, -- Julien Grall