Re: [PATCH v4 11/16] xen/arm: calculate vgic irq rank based on register size

[Julien Grall <julien.grall@linaro.org>]

Hi Vijay,

On 05/26/2014 11:26 AM, vijay.kilari@gmail.com wrote:
> -        *r = ( (v->domain->max_vcpus<<5) & GICD_TYPE_CPUS )
> -            |( ((v->domain->arch.vgic.nr_lines/32)) & GICD_TYPE_LINES );
> +        *r = ( (v->domain->max_vcpus << 5) & GICD_TYPE_CPUS )
> +            |( ((v->domain->arch.vgic.nr_lines / 32)) & GICD_TYPE_LINES );

Why these changes?

>          vgic_unlock(v);
>          return 1;
>      case GICD_IIDR:
> -        if ( dabt.size != 2 ) goto bad_width;
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
>          /*
>           * XXX Do we need a JEP106 manufacturer ID?
>           * Just use the physical h/w value for now
> @@ -119,8 +119,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
>          goto read_as_zero;
>  
>      case GICD_ISENABLER ... GICD_ISENABLERN:
> -        if ( dabt.size != 2 ) goto bad_width;
> -        rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER);
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);

In your commit message you explicitly say that use DABT_* will help you
to get the register offset but... you still hardcode the size.

Why can't you use dabt.size here? And all the other places.

Regards,

-- 
Julien Grall