From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH v4 11/16] xen/arm: calculate vgic irq rank
 based on register size
Date: Fri, 30 May 2014 10:58:49 +0100
Message-ID: <53885659.1050903@linaro.org>
References: <1401100009-7326-1-git-send-email-vijay.kilari@gmail.com>	<1401100009-7326-12-git-send-email-vijay.kilari@gmail.com>	<53847D81.7000005@linaro.org>
	<CALicx6vw-c1dPJMZo=JyrxDHV67FyTx2HkgW_RbeWc51XLVpww@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; Format="flowed"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
In-Reply-To: <CALicx6vw-c1dPJMZo=JyrxDHV67FyTx2HkgW_RbeWc51XLVpww@mail.gmail.com>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Vijay Kilari <vijay.kilari@gmail.com>
Cc: Ian Campbell <Ian.Campbell@citrix.com>, Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Prasun Kapoor <Prasun.Kapoor@caviumnetworks.com>, Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>, Stefano Stabellini <stefano.stabellini@citrix.com>
List-Id: xen-devel@lists.xenproject.org

Hi Vijay,

On 30/05/14 09:59, Vijay Kilari wrote:
> On Tue, May 27, 2014 at 5:26 PM, Julien Grall <julien.grall@linaro.org> wrote:
>> On 05/26/2014 11:26 AM, vijay.kilari@gmail.com wrote:
>>> -        *r = ( (v->domain->max_vcpus<<5) & GICD_TYPE_CPUS )
>>> -            |( ((v->domain->arch.vgic.nr_lines/32)) & GICD_TYPE_LINES );
>>> +        *r = ( (v->domain->max_vcpus << 5) & GICD_TYPE_CPUS )
>>> +            |( ((v->domain->arch.vgic.nr_lines / 32)) & GICD_TYPE_LINES );
>>
>> Why these changes?
>
> Legacy coding style fixes.

If you don't touch that part of the code, please don't do random coding 
style fix without any mention in the commit message.

>
>>
>>>           vgic_unlock(v);
>>>           return 1;
>>>       case GICD_IIDR:
>>> -        if ( dabt.size != 2 ) goto bad_width;
>>> +        if ( dabt.size != DABT_WORD ) goto bad_width;
>>>           /*
>>>            * XXX Do we need a JEP106 manufacturer ID?
>>>            * Just use the physical h/w value for now
>>> @@ -119,8 +119,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
>>>           goto read_as_zero;
>>>
>>>       case GICD_ISENABLER ... GICD_ISENABLERN:
>>> -        if ( dabt.size != 2 ) goto bad_width;
>>> -        rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER);
>>> +        if ( dabt.size != DABT_WORD ) goto bad_width;
>>> +        rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
>>
>> In your commit message you explicitly say that use DABT_* will help you
>> to get the register offset but... you still hardcode the size.
>>
>> Why can't you use dabt.size here? And all the other places.
>
>     dabt.size gives the current register access size but not the actual
> register size.

In this specific case, the register access size and the actual register 
size is the same...

Regards,

-- 
Julien Grall