From: "Jan Beulich" <jbeulich@suse.com>
To: ian.campbell@citrix.com
Cc: george.dunlap@eu.citrix.com, andrew.cooper3@citrix.com,
will.auld@intel.com, xen-devel@lists.xen.org,
dongxiao.xu@intel.com, jun.nakajima@intel.com
Subject: Re: Xen Platform QoS design discussion
Date: Fri, 30 May 2014 12:17:30 +0100 [thread overview]
Message-ID: <538876DA02000078000B5403@mail.emea.novell.com> (raw)
In-Reply-To: <1401441052.15871.55.camel@hastur.hellion.org.uk>
>>> Ian Campbell <ian.campbell@citrix.com> 05/30/14 11:11 AM >>>
>On Thu, 2014-05-29 at 10:11 +0100, Jan Beulich wrote:
>> >>> "Xu, Dongxiao" <dongxiao.xu@intel.com> 05/29/14 9:31 AM >>>
>> >Okay. If I understand correctly, you prefer to implement a pure MSR access
>> >hypercall for one CPU, and put all other CQM things in libxc/libxl layer.
>>
>> >In this case, if libvert/XenAPI is trying to query a domain's cache utilization
>> >in the system (say 2 sockets), then it will trigger _two_ such MSR access
>> >hypercalls for CPUs in the 2 different sockets.
>> >If you are okay with this idea, I am going to implement it.
>>
>> I am okay with it, but give it a couple of days before you start so that others
>> can voice their opinions too.
>
>Dom0 may not have a vcpu which is scheduled/schedulable on every socket.
>scheduled it can probably deal with by doing awful sounding temporary
>things to its affinity mask, but if it is not schedulable (e.g. due to
>cpupools etc) then that sounds even harder to sort...
But that's why we're intending to add a helper hypercall in the first place. This
isn't intended to be a 'read MSR' one, but a 'read MSR in this CPU'.
Jan
next prev parent reply other threads:[~2014-05-30 11:17 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-30 16:47 Xen Platform QoS design discussion Xu, Dongxiao
2014-04-30 17:02 ` Ian Campbell
2014-05-01 0:56 ` Xu, Dongxiao
2014-05-02 9:23 ` Jan Beulich
2014-05-02 12:30 ` Xu, Dongxiao
2014-05-02 12:40 ` Jan Beulich
2014-05-04 0:46 ` Xu, Dongxiao
2014-05-06 9:10 ` Ian Campbell
2014-05-06 1:40 ` Xu, Dongxiao
2014-05-06 7:55 ` Jan Beulich
2014-05-06 10:06 ` Andrew Cooper
2014-05-07 2:08 ` Xu, Dongxiao
2014-05-07 9:10 ` Ian Campbell
2014-05-07 13:26 ` George Dunlap
2014-05-07 21:18 ` Andrew Cooper
2014-05-08 5:21 ` Xu, Dongxiao
2014-05-08 11:25 ` Andrew Cooper
2014-05-09 2:41 ` Xu, Dongxiao
2014-05-13 1:53 ` Xu, Dongxiao
2014-05-16 5:11 ` Xu, Dongxiao
2014-05-19 11:28 ` George Dunlap
2014-05-19 11:45 ` Jan Beulich
2014-05-19 12:13 ` George Dunlap
2014-05-19 12:41 ` Jan Beulich
2014-05-22 8:19 ` Xu, Dongxiao
2014-05-22 8:39 ` Jan Beulich
2014-05-22 9:27 ` George Dunlap
2014-05-26 0:51 ` Xu, Dongxiao
2014-05-29 0:45 ` Xu, Dongxiao
2014-05-29 7:01 ` Jan Beulich
2014-05-29 7:31 ` Xu, Dongxiao
2014-05-29 9:11 ` Jan Beulich
2014-05-30 9:10 ` Ian Campbell
2014-05-30 11:17 ` Jan Beulich [this message]
2014-05-30 12:33 ` Ian Campbell
2014-06-05 0:48 ` Xu, Dongxiao
2014-06-05 10:43 ` George Dunlap
2014-05-29 9:13 ` Andrew Cooper
2014-05-30 1:07 ` Xu, Dongxiao
2014-05-30 6:23 ` Jan Beulich
2014-05-30 7:51 ` Xu, Dongxiao
2014-05-30 11:15 ` Jan Beulich
2014-05-02 12:50 ` Andrew Cooper
2014-05-04 2:34 ` Xu, Dongxiao
2014-05-06 9:12 ` Ian Campbell
2014-05-06 10:00 ` Andrew Cooper
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