From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v2 1/2] xen/arm: ignore guest writes to GICD_ITARGETSR for SPIs Date: Tue, 03 Jun 2014 17:25:46 +0100 Message-ID: <538DF70A.3090306@linaro.org> References: <1401811627-4389-1-git-send-email-stefano.stabellini@eu.citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1401811627-4389-1-git-send-email-stefano.stabellini@eu.citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini , xen-devel@lists.xensource.com Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com List-Id: xen-devel@lists.xenproject.org Hi Stefano, On 06/03/2014 05:07 PM, Stefano Stabellini wrote: > Ignore guest writes to GICD_ITARGETSR that set the target cpu to a cpu > other than cpu0 for SPIs. > > Also ignore guest writes to GICD_ITARGETSR for PPIs and SGIs as they can > only be delivered to the same cpu and that has already been configured > at initialization time. > > Signed-off-by: Stefano Stabellini > > --- > > Changes in v2: > - ignore writes to rank 0; > - don't print a warning for ignoring writes to GICD_ITARGETSR; > - add a comment in the code to remember that we don't implement writes > to GICD_ITARGETSR. > --- > xen/arch/arm/vgic.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c > index cb8df3a..1304b5e 100644 > --- a/xen/arch/arm/vgic.c > +++ b/xen/arch/arm/vgic.c > @@ -584,6 +584,13 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info) > if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width; > rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR); > if ( rank == NULL) goto write_ignore; > + /* only same vcpu delivery can be allowed for PPIs and SGIs */ > + if ( REG_RANK_NR(8, gicd_reg - GICD_ITARGETSR) == 0 ) > + return 1; This test is wrong. PPIs and SGIs are already a preset value (see vcpu_vgic_init). Futhermore, there is already a specific case for PPIs and SGIs (see few lines above). > + /* SPI delivery to secondary vcpus is unimplemented */ > + if ( REG_RANK_NR(8, gicd_reg - GICD_ITARGETSR) > 0 && > + *r != (1|1<<8|1<<16|1<<24) ) > + return 1; You don't handle byte-access here. Rather than testing the value, I think it's fine to return unconditionally. > vgic_lock_rank(v, rank); > if ( dabt.size == 2 ) > rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r; > Regards, -- Julien Grall