From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v4 1/4] xen/arm: observe itargets setting in vgic_enable_irqs and vgic_disable_irqs Date: Mon, 09 Jun 2014 12:37:23 +0100 Message-ID: <53959C73.3030300@linaro.org> References: <1402076908-26740-1-git-send-email-stefano.stabellini@eu.citrix.com> <539322D3.8040504@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini Cc: julien.grall@citrix.com, xen-devel@lists.xensource.com, Ian.Campbell@citrix.com List-Id: xen-devel@lists.xenproject.org On 06/09/2014 11:47 AM, Stefano Stabellini wrote: >> Write in GICD_ITARGETSR can be either half-word or word. If I'm not mistaken >> you sanity check only handle word access. > > I realize that it is a bit tricky to read, but this works for both word > and half-word accesses. I think you have to mask the unused bits in the register. We can't assume that they will be all-zeroed. Regards, -- Julien Grall