From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Vrabel Subject: Re: [PATCH v2 4/6] xen/PMU: Describe vendor-specific PMU registers Date: Tue, 10 Jun 2014 15:11:57 +0100 Message-ID: <5397122D.2000908@citrix.com> References: <1402076686-26586-1-git-send-email-boris.ostrovsky@oracle.com> <1402076686-26586-5-git-send-email-boris.ostrovsky@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1402076686-26586-5-git-send-email-boris.ostrovsky@oracle.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Boris Ostrovsky , konrad.wilk@oracle.com Cc: kevin.tian@intel.com, dietmar.hahn@ts.fujitsu.com, JBeulich@suse.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 06/06/14 18:44, Boris Ostrovsky wrote: > AMD and Intel PMU register initialization and helpers that determine whether a > register belongs to PMU. > > This and some of subsequent PMU emulation code is somewhat similar to Xen's PMU > implementation. This and patches 5 and 6 look ok but they seem to be split somewhat arbitrarily. Is it still bisectable as-is? David