From: Julien Grall <julien.grall@linaro.org>
To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
Ian Campbell <Ian.Campbell@citrix.com>
Cc: julien.grall@citrix.com, xen-devel@lists.xensource.com
Subject: Re: [PATCH v4 2/4] xen/arm: inflight irqs during migration
Date: Wed, 11 Jun 2014 15:28:50 +0100 [thread overview]
Message-ID: <539867A2.4060405@linaro.org> (raw)
In-Reply-To: <alpine.DEB.2.02.1406111351440.13771@kaball.uk.xensource.com>
On 06/11/2014 03:15 PM, Stefano Stabellini wrote:
>>> + {
>>> + unsigned int irq, target, old_target;
>>> + struct vcpu *v_target, *v_old;
>>> +
>>> + target = i % 8;
>>> +
>>> + irq = offset + (i / 8);
>>> + v_target = v->domain->vcpu[target];
>>> + old_target = byte_read(rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)], 0, i/8);
>>> + v_old = v->domain->vcpu[old_target];
>>
>> v_target and v_old might be the same.
>
> No, they could not: if they were find_next_bit wouldn't find the bit set.
Even though v_target is always != v_old (because of the tr = r & ~val
stuff), why do you migrate if the old_target will be in the new mask?
BTW, this code suffers the same issue as #1, i.e this register can be
accessed by byte.
Regards,
--
Julien Grall
next prev parent reply other threads:[~2014-06-11 14:28 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-06 17:47 [PATCH v4 0/4] vgic emulation and GICD_ITARGETSR Stefano Stabellini
2014-06-06 17:48 ` [PATCH v4 1/4] xen/arm: observe itargets setting in vgic_enable_irqs and vgic_disable_irqs Stefano Stabellini
2014-06-07 14:33 ` Julien Grall
2014-06-09 10:47 ` Stefano Stabellini
2014-06-09 11:37 ` Julien Grall
2014-06-09 12:04 ` Stefano Stabellini
2014-06-09 12:32 ` Julien Grall
2014-06-09 17:21 ` Stefano Stabellini
2014-06-10 11:44 ` Ian Campbell
2014-06-11 11:54 ` Stefano Stabellini
2014-06-06 17:48 ` [PATCH v4 2/4] xen/arm: inflight irqs during migration Stefano Stabellini
2014-06-10 12:12 ` Ian Campbell
2014-06-11 14:15 ` Stefano Stabellini
2014-06-11 14:28 ` Julien Grall [this message]
2014-06-11 14:49 ` Stefano Stabellini
2014-06-11 15:16 ` Julien Grall
2014-06-11 15:55 ` Stefano Stabellini
2014-06-06 17:48 ` [PATCH v4 3/4] xen/arm: support irq delivery to vcpu > 0 Stefano Stabellini
2014-06-10 12:16 ` Ian Campbell
2014-06-10 12:56 ` Julien Grall
2014-06-11 14:22 ` Stefano Stabellini
2014-06-06 17:48 ` [PATCH v4 4/4] xen/arm: physical irq follow virtual irq Stefano Stabellini
2014-06-10 12:27 ` Ian Campbell
2014-06-11 14:47 ` Stefano Stabellini
2014-06-11 15:14 ` Ian Campbell
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