From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH 5/5] xen: arm: flush TLB after overwriting
 1:1 mapping in boot page tables
Date: Wed, 16 Jul 2014 19:11:23 +0100
Message-ID: <53C6C04B.6070809@linaro.org>
References: <1405355930.31863.5.camel@kazak.uk.xensource.com>
	<1405355950-6461-5-git-send-email-ian.campbell@citrix.com>
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Cc: tim@xen.org, stefano.stabellini@eu.citrix.com
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Hi Ian,

On 14/07/14 17:39, Ian Campbell wrote:
> Otherwise a stale TLB entry can shadow the fixmap/UART or DTB mapping
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>

Good catch! I guess this could also happen on Xen 4.4. I would consider 
to backport it :)

Acked-by: Julien Grall <julien.grall@linaro.org>

Regards,

-- 
Julien Grall