* [PATCH v7 0/5] xen/arm: Add GICv3 support
@ 2014-07-11 12:51 vijay.kilari
2014-07-11 12:51 ` [PATCH v7 1/5] xen/arm: Add support for GIC v3 vijay.kilari
` (5 more replies)
0 siblings, 6 replies; 38+ messages in thread
From: vijay.kilari @ 2014-07-11 12:51 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, manish.jaggi, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Add GICv3 support for arm64 platform.
>From v6 version, this patch series is split into v6a and v6.
All the GICv2 and VGIC code refactoring patches of v6a are merged.
The GICv3 patches as v7 series are posted here.
Tested with ARM64 simulator with multicore core
and booted Dom0 kernel.
Major changes in v7:
- Introduced vgic callback to handle sysreg emulation
- Coding style fixes
- undef64_exception instead of undef_exception for sysreg error
Major changes in v6:
- Added read_apr() to read ICH_APRn in GICv3
- Added asserts
- PIDR2 check for architecture value
- Remove update_cpu_lr_mask call
- Changed parameter ordering for gicv3_send_sgi()
- Save and restore ICC_SRE_EL1 register
- Computed cpumask in gicv3_send_sgi() function
Major changes in v5:
- Introduced new patch for checking platform capability for gicv3
- Introduced more patches for vgic clean up and code movement
- Added synchronization barriers and clean up in GICv3 driver
- Rebase on top of master branch +
remotes/origin/no_maintenance_interrupts-v8 patch set
- Code base available in github
git clone https://github.com/vijaykilari/Xen-GICv3.git
- Fixed comments and coding style
Major changes in v4:
- Changed io handlers to take mmio address and size as
parameters
- ioremap is used instead of fixmap to map GICv2 address
space. Removed /4 in GICv2 register definitions
- vGIC driver now uses register size to calculate IRQ rank
- GICv2 LR register definitions are declared locally in GICv2 driver
- GICR & GICD common register handling in vgic-v3 driver are segregated
in one common function
- irq_hw_controller definition is managed in GICv2 and GICv3 drivers
- Made irq_ops const
- GIC DT node is updated in respective drivers
- Comments and coding style fixes
- Rebased on remotes/origin/no_maintenance_interrupts-v8 + Julien's
patch set
Major changes in v3:
- Moved io.h from xen/arch/arm to xen/include/asm-arm
and renamed as mmio.h
- Made all the io handlers as domain specific and removed
check handlers. Instead address and size are passed
- Cleaned up sgi handling functions in V2 gic driver and
made generic
- Removed unused parameters in do_sgi call
- VGIC driver is chosen based on GIC driver initialized
- Implemented SGI handling for GICv3 to boot multicore
- Missing coding style fixes
- Rebased to remotes/origin/no_maintenance_interrupts-v6
branch of Stephano's unstable tree
Major Changes in v2:
- Added per domain io handler
- Use device api to initialize gic driver
- Avoid use of void pointer to access common data
- Moved vgic address information data from domain.h
- Coding style
Vijaya Kumar K (5):
xen/arm: Add support for GIC v3
xen/arm: Add virtual GICv3 support
xen/arm: Update Dom0 GIC dt node with GICv3 information
xen/arm: add SGI handling for GICv3
xen/arm: check for GICv3 platform support
xen/arch/arm/Makefile | 2 +
xen/arch/arm/domain_build.c | 47 +-
xen/arch/arm/gic-v2.c | 51 ++
xen/arch/arm/gic-v3.c | 1262 +++++++++++++++++++++++++++++++++++++
xen/arch/arm/gic.c | 6 +
xen/arch/arm/setup.c | 5 +-
xen/arch/arm/traps.c | 15 +
xen/arch/arm/vgic-v2.c | 8 +-
xen/arch/arm/vgic-v3.c | 954 ++++++++++++++++++++++++++++
xen/arch/arm/vgic.c | 12 +
xen/include/asm-arm/cpufeature.h | 1 +
xen/include/asm-arm/domain.h | 8 +
xen/include/asm-arm/gic.h | 24 +
xen/include/asm-arm/gic_v3_defs.h | 166 +++++
xen/include/asm-arm/processor.h | 19 +-
xen/include/asm-arm/sysregs.h | 3 +
xen/include/asm-arm/vgic.h | 16 +-
xen/include/xen/lib.h | 2 +
18 files changed, 2546 insertions(+), 55 deletions(-)
create mode 100644 xen/arch/arm/gic-v3.c
create mode 100644 xen/arch/arm/vgic-v3.c
create mode 100644 xen/include/asm-arm/gic_v3_defs.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-11 12:51 [PATCH v7 0/5] xen/arm: Add GICv3 support vijay.kilari
@ 2014-07-11 12:51 ` vijay.kilari
2014-07-16 11:41 ` Ian Campbell
2014-07-11 12:51 ` [PATCH v7 2/5] xen/arm: Add virtual GICv3 support vijay.kilari
` (4 subsequent siblings)
5 siblings, 1 reply; 38+ messages in thread
From: vijay.kilari @ 2014-07-11 12:51 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, manish.jaggi, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Add support for GIC v3 specification System register access(SRE)
is enabled to access cpu and virtual interface registers based
on kernel GICv3 driver.
GICv3 driver uses macros for size values similar to kernel's
include/linux/sizes.h file. Introduces required macros in lib.h
This patch adds only basic v3 support.
Does not support Interrupt Translation support (ITS)
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
v7: Fixed wrong check for irq number in gicv3_set_irq_properties.
Introduced panic during cpu_init on wrong priority bits.
Changes in v6:
- Added read_apr() to read ICH_APRn in GICv3
- Added asserts
- PIDR2 check for architecture value
- Remove update_cpu_lr_mask call
- Changed parameter ordering for gicv3_send_sgi()
- Save and restore ICC_SRE_EL1 register
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/gic-v3.c | 1177 +++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/domain.h | 8 +
xen/include/asm-arm/gic.h | 20 +
xen/include/asm-arm/gic_v3_defs.h | 159 +++++
xen/include/asm-arm/processor.h | 14 +
xen/include/xen/lib.h | 2 +
7 files changed, 1381 insertions(+)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 20f59f4..1684c09 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -11,6 +11,7 @@ obj-y += domctl.o
obj-y += sysctl.o
obj-y += domain_build.o
obj-y += gic.o gic-v2.o
+obj-$(CONFIG_ARM_64) += gic-v3.o
obj-y += io.o
obj-y += irq.o
obj-y += kernel.o
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
new file mode 100644
index 0000000..473dd88
--- /dev/null
+++ b/xen/arch/arm/gic-v3.c
@@ -0,0 +1,1177 @@
+/*
+ * xen/arch/arm/gic-v3.c
+ *
+ * ARM Generic Interrupt Controller support v3 version
+ * based on xen/arch/arm/gic-v2.c and kernel GICv3 driver
+ *
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>, Cavium Inc
+ * ported to Xen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/cpu.h>
+#include <xen/mm.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+#include <xen/errno.h>
+#include <xen/delay.h>
+#include <xen/device_tree.h>
+#include <asm/p2m.h>
+#include <asm/domain.h>
+#include <asm/io.h>
+#include <asm/device.h>
+#include <asm/gic.h>
+#include <asm/gic_v3_defs.h>
+
+struct rdist_region {
+ paddr_t base;
+ paddr_t size;
+ void __iomem *map_base;
+};
+
+/* Global state */
+static struct {
+ paddr_t dbase; /* Address of distributor registers */
+ paddr_t dbase_size;
+ void __iomem *map_dbase; /* Mapped address of distributor registers */
+ struct rdist_region *rdist_regions;
+ uint32_t rdist_stride;
+ unsigned int rdist_count; /* Number of rdist regions count */
+ unsigned int nr_priorities;
+ spinlock_t lock;
+} gicv3;
+
+static struct gic_info gicv3_info;
+
+/* per-cpu re-distributor base */
+static DEFINE_PER_CPU(void __iomem*, rbase);
+
+#define GICD (gicv3.map_dbase)
+#define GICD_RDIST_BASE (this_cpu(rbase))
+#define GICD_RDIST_SGI_BASE (GICD_RDIST_BASE + SZ_64K)
+
+/*
+ * Saves all 16(Max) LR registers. Though number of LRs implemented
+ * is implementation specific.
+ */
+static inline void gicv3_save_lrs(int nr_lrs, struct vcpu *v)
+{
+ /* Fall through for all the cases */
+ switch ( nr_lrs )
+ {
+ case 16:
+ v->arch.gic.v3.lr[15] = READ_SYSREG(ICH_LR15_EL2);
+ case 15:
+ v->arch.gic.v3.lr[14] = READ_SYSREG(ICH_LR14_EL2);
+ case 14:
+ v->arch.gic.v3.lr[13] = READ_SYSREG(ICH_LR13_EL2);
+ case 13:
+ v->arch.gic.v3.lr[12] = READ_SYSREG(ICH_LR12_EL2);
+ case 12:
+ v->arch.gic.v3.lr[11] = READ_SYSREG(ICH_LR11_EL2);
+ case 11:
+ v->arch.gic.v3.lr[10] = READ_SYSREG(ICH_LR10_EL2);
+ case 10:
+ v->arch.gic.v3.lr[9] = READ_SYSREG(ICH_LR9_EL2);
+ case 9:
+ v->arch.gic.v3.lr[8] = READ_SYSREG(ICH_LR8_EL2);
+ case 8:
+ v->arch.gic.v3.lr[7] = READ_SYSREG(ICH_LR7_EL2);
+ case 7:
+ v->arch.gic.v3.lr[6] = READ_SYSREG(ICH_LR6_EL2);
+ case 6:
+ v->arch.gic.v3.lr[5] = READ_SYSREG(ICH_LR5_EL2);
+ case 5:
+ v->arch.gic.v3.lr[4] = READ_SYSREG(ICH_LR4_EL2);
+ case 4:
+ v->arch.gic.v3.lr[3] = READ_SYSREG(ICH_LR3_EL2);
+ case 3:
+ v->arch.gic.v3.lr[2] = READ_SYSREG(ICH_LR2_EL2);
+ case 2:
+ v->arch.gic.v3.lr[1] = READ_SYSREG(ICH_LR1_EL2);
+ case 1:
+ v->arch.gic.v3.lr[0] = READ_SYSREG(ICH_LR0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+/*
+ * Restores all 16(Max) LR registers. Though number of LRs implemented
+ * is implementation specific.
+ */
+static inline void gicv3_restore_lrs(int nr_lrs, const struct vcpu *v)
+{
+ /* Fall through for all the cases */
+ switch ( nr_lrs )
+ {
+ case 16:
+ WRITE_SYSREG(v->arch.gic.v3.lr[15], ICH_LR15_EL2);
+ case 15:
+ WRITE_SYSREG(v->arch.gic.v3.lr[14], ICH_LR14_EL2);
+ case 14:
+ WRITE_SYSREG(v->arch.gic.v3.lr[13], ICH_LR13_EL2);
+ case 13:
+ WRITE_SYSREG(v->arch.gic.v3.lr[12], ICH_LR12_EL2);
+ case 12:
+ WRITE_SYSREG(v->arch.gic.v3.lr[11], ICH_LR11_EL2);
+ case 11:
+ WRITE_SYSREG(v->arch.gic.v3.lr[10], ICH_LR10_EL2);
+ case 10:
+ WRITE_SYSREG(v->arch.gic.v3.lr[9], ICH_LR9_EL2);
+ case 9:
+ WRITE_SYSREG(v->arch.gic.v3.lr[8], ICH_LR8_EL2);
+ case 8:
+ WRITE_SYSREG(v->arch.gic.v3.lr[7], ICH_LR7_EL2);
+ case 7:
+ WRITE_SYSREG(v->arch.gic.v3.lr[6], ICH_LR6_EL2);
+ case 6:
+ WRITE_SYSREG(v->arch.gic.v3.lr[5], ICH_LR5_EL2);
+ case 5:
+ WRITE_SYSREG(v->arch.gic.v3.lr[4], ICH_LR4_EL2);
+ case 4:
+ WRITE_SYSREG(v->arch.gic.v3.lr[3], ICH_LR3_EL2);
+ case 3:
+ WRITE_SYSREG(v->arch.gic.v3.lr[2], ICH_LR2_EL2);
+ case 2:
+ WRITE_SYSREG(v->arch.gic.v3.lr[1], ICH_LR1_EL2);
+ case 1:
+ WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static uint64_t gicv3_ich_read_lr(int lr)
+{
+ switch ( lr )
+ {
+ case 0: return READ_SYSREG(ICH_LR0_EL2);
+ case 1: return READ_SYSREG(ICH_LR1_EL2);
+ case 2: return READ_SYSREG(ICH_LR2_EL2);
+ case 3: return READ_SYSREG(ICH_LR3_EL2);
+ case 4: return READ_SYSREG(ICH_LR4_EL2);
+ case 5: return READ_SYSREG(ICH_LR5_EL2);
+ case 6: return READ_SYSREG(ICH_LR6_EL2);
+ case 7: return READ_SYSREG(ICH_LR7_EL2);
+ case 8: return READ_SYSREG(ICH_LR8_EL2);
+ case 9: return READ_SYSREG(ICH_LR9_EL2);
+ case 10: return READ_SYSREG(ICH_LR10_EL2);
+ case 11: return READ_SYSREG(ICH_LR11_EL2);
+ case 12: return READ_SYSREG(ICH_LR12_EL2);
+ case 13: return READ_SYSREG(ICH_LR13_EL2);
+ case 14: return READ_SYSREG(ICH_LR14_EL2);
+ case 15: return READ_SYSREG(ICH_LR15_EL2);
+ default:
+ BUG();
+ }
+}
+
+static void gicv3_ich_write_lr(int lr, uint64_t val)
+{
+ switch ( lr )
+ {
+ case 0:
+ WRITE_SYSREG(val, ICH_LR0_EL2);
+ break;
+ case 1:
+ WRITE_SYSREG(val, ICH_LR1_EL2);
+ break;
+ case 2:
+ WRITE_SYSREG(val, ICH_LR2_EL2);
+ break;
+ case 3:
+ WRITE_SYSREG(val, ICH_LR3_EL2);
+ break;
+ case 4:
+ WRITE_SYSREG(val, ICH_LR4_EL2);
+ break;
+ case 5:
+ WRITE_SYSREG(val, ICH_LR5_EL2);
+ break;
+ case 6:
+ WRITE_SYSREG(val, ICH_LR6_EL2);
+ break;
+ case 7:
+ WRITE_SYSREG(val, ICH_LR7_EL2);
+ break;
+ case 8:
+ WRITE_SYSREG(val, ICH_LR8_EL2);
+ break;
+ case 9:
+ WRITE_SYSREG(val, ICH_LR9_EL2);
+ break;
+ case 10:
+ WRITE_SYSREG(val, ICH_LR10_EL2);
+ break;
+ case 11:
+ WRITE_SYSREG(val, ICH_LR11_EL2);
+ break;
+ case 12:
+ WRITE_SYSREG(val, ICH_LR12_EL2);
+ break;
+ case 13:
+ WRITE_SYSREG(val, ICH_LR13_EL2);
+ break;
+ case 14:
+ WRITE_SYSREG(val, ICH_LR14_EL2);
+ break;
+ case 15:
+ WRITE_SYSREG(val, ICH_LR15_EL2);
+ break;
+ default:
+ return;
+ }
+ isb();
+}
+
+/*
+ * System Register Enable (SRE). Enable to access CPU & Virtual
+ * interface registers as system registers in EL2
+ */
+static void gicv3_enable_sre(void)
+{
+ uint32_t val;
+
+ val = READ_SYSREG32(ICC_SRE_EL2);
+ val |= GICC_SRE_EL2_SRE | GICC_SRE_EL2_ENEL1;
+
+ WRITE_SYSREG32(val, ICC_SRE_EL2);
+ isb();
+}
+
+/* Wait for completion of a distributor change */
+static void gicv3_do_wait_for_rwp(void __iomem *base)
+{
+ uint32_t val;
+ bool_t timeout = 0;
+ s_time_t deadline = NOW() + MILLISECS(1000);
+
+ do {
+ val = readl_relaxed(base + GICD_CTLR);
+ if ( !(val & GICD_CTLR_RWP) )
+ break;
+ if ( NOW() > deadline )
+ {
+ timeout = 1;
+ break;
+ }
+ cpu_relax();
+ udelay(1);
+ } while ( 1 );
+
+ if ( timeout )
+ dprintk(XENLOG_ERR, "RWP timeout\n");
+}
+
+static void gicv3_dist_wait_for_rwp(void)
+{
+ gicv3_do_wait_for_rwp(GICD);
+}
+
+static void gicv3_redist_wait_for_rwp(void)
+{
+ gicv3_do_wait_for_rwp(GICD_RDIST_BASE);
+}
+
+static void gicv3_wait_for_rwp(int irq)
+{
+ if ( irq < NR_LOCAL_IRQS )
+ gicv3_redist_wait_for_rwp();
+ else
+ gicv3_dist_wait_for_rwp();
+}
+
+static unsigned int gicv3_get_cpu_from_mask(const cpumask_t *cpumask)
+{
+ unsigned int cpu;
+ cpumask_t possible_mask;
+
+ cpumask_and(&possible_mask, cpumask, &cpu_possible_map);
+ cpu = cpumask_any(&possible_mask);
+
+ return cpu;
+}
+
+static void restore_aprn_regs(const union gic_state_data *d)
+{
+ /* Write APRn register based on number of priorities
+ platform has implemented */
+ switch ( gicv3.nr_priorities )
+ {
+ case 7:
+ WRITE_SYSREG32(d->v3.apr0[2], ICH_AP0R2_EL2);
+ WRITE_SYSREG32(d->v3.apr1[2], ICH_AP1R2_EL2);
+ /* Fall through */
+ case 6:
+ WRITE_SYSREG32(d->v3.apr0[1], ICH_AP0R1_EL2);
+ WRITE_SYSREG32(d->v3.apr1[1], ICH_AP1R1_EL2);
+ /* Fall through */
+ case 5:
+ WRITE_SYSREG32(d->v3.apr0[0], ICH_AP0R0_EL2);
+ WRITE_SYSREG32(d->v3.apr1[0], ICH_AP1R0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static void save_aprn_regs(union gic_state_data *d)
+{
+ /* Read APRn register based on number of priorities
+ platform has implemented */
+ switch ( gicv3.nr_priorities )
+ {
+ case 7:
+ d->v3.apr0[2] = READ_SYSREG32(ICH_AP0R2_EL2);
+ d->v3.apr1[2] = READ_SYSREG32(ICH_AP1R2_EL2);
+ /* Fall through */
+ case 6:
+ d->v3.apr0[1] = READ_SYSREG32(ICH_AP0R1_EL2);
+ d->v3.apr1[1] = READ_SYSREG32(ICH_AP1R1_EL2);
+ /* Fall through */
+ case 5:
+ d->v3.apr0[0] = READ_SYSREG32(ICH_AP0R0_EL2);
+ d->v3.apr1[0] = READ_SYSREG32(ICH_AP1R0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static void gicv3_save_state(struct vcpu *v)
+{
+
+ /* No need for spinlocks here because interrupts are disabled around
+ * this call and it only accesses struct vcpu fields that cannot be
+ * accessed simultaneously by another pCPU.
+ *
+ * Make sure all stores to the GIC via the memory mapped interface
+ * are now visible to the system register interface
+ */
+ dsb(sy);
+ gicv3_save_lrs(gicv3_info.nr_lrs, v);
+ save_aprn_regs(&v->arch.gic);
+ v->arch.gic.v3.vmcr = READ_SYSREG32(ICH_VMCR_EL2);
+ v->arch.gic.v3.sre_el1 = READ_SYSREG32(ICC_SRE_EL1);
+}
+
+static void gicv3_restore_state(const struct vcpu *v)
+{
+ WRITE_SYSREG32(v->arch.gic.v3.sre_el1, ICC_SRE_EL1);
+ WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2);
+ restore_aprn_regs(&v->arch.gic);
+ gicv3_restore_lrs(gicv3_info.nr_lrs, v);
+
+ /*
+ * Make sure all stores are visible the GIC
+ */
+ dsb(sy);
+}
+
+static void gicv3_dump_state(const struct vcpu *v)
+{
+ int i;
+
+ if ( v == current )
+ {
+ for ( i = 0; i < gicv3_info.nr_lrs; i++ )
+ printk(" HW_LR[%d]=%lx\n", i, gicv3_ich_read_lr(i));
+ }
+ else
+ {
+ for ( i = 0; i < gicv3_info.nr_lrs; i++ )
+ printk(" VCPU_LR[%d]=%lx\n", i, v->arch.gic.v3.lr[i]);
+ }
+}
+
+static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset)
+{
+ u32 mask = 1 << (irqd->irq % 32);
+ void __iomem *base;
+
+ if ( irqd->irq < NR_GIC_LOCAL_IRQS )
+ base = GICD_RDIST_SGI_BASE;
+ else
+ base = GICD;
+
+ writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
+ gicv3_wait_for_rwp(irqd->irq);
+}
+
+static void gicv3_unmask_irq(struct irq_desc *irqd)
+{
+ gicv3_poke_irq(irqd, GICD_ISENABLER);
+}
+
+static void gicv3_mask_irq(struct irq_desc *irqd)
+{
+ gicv3_poke_irq(irqd, GICD_ICENABLER);
+}
+
+static void gicv3_eoi_irq(struct irq_desc *irqd)
+{
+ /* Lower the priority */
+ WRITE_SYSREG32(irqd->irq, ICC_EOIR1_EL1);
+ isb();
+}
+
+static void gicv3_dir_irq(struct irq_desc *irqd)
+{
+ /* Deactivate */
+ WRITE_SYSREG32(irqd->irq, ICC_DIR_EL1);
+ isb();
+}
+
+static unsigned int gicv3_read_irq(void)
+{
+ return (READ_SYSREG32(ICC_IAR1_EL1) & GICC_IA_IRQ);
+}
+
+static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
+{
+ uint64_t mpidr = cpu_logical_map(cpu);
+ return (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
+static void gicv3_set_irq_properties(struct irq_desc *desc,
+ const cpumask_t *cpu_mask,
+ unsigned int priority)
+{
+ uint32_t cfg, edgebit;
+ uint64_t affinity;
+ void __iomem *base;
+ unsigned int cpu = gicv3_get_cpu_from_mask(cpu_mask);
+ unsigned int irq = desc->irq;
+ unsigned int type = desc->arch.type;
+
+ /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
+ ASSERT(irq >= NR_GIC_SGI);
+
+ spin_lock(&gicv3.lock);
+
+ if ( irq >= NR_GIC_LOCAL_IRQS)
+ base = GICD + GICD_ICFGR + (irq / 16) * 4;
+ else
+ base = GICD_RDIST_SGI_BASE + GICR_ICFGR1;
+
+ cfg = readl_relaxed(base);
+
+ edgebit = 2u << (2 * (irq % 16));
+ if ( type & DT_IRQ_TYPE_LEVEL_MASK )
+ cfg &= ~edgebit;
+ else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
+ cfg |= edgebit;
+
+ writel_relaxed(cfg, base);
+
+ affinity = gicv3_mpidr_to_affinity(cpu);
+ /* Make sure we don't broadcast the interrupt */
+ affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
+
+ if ( irq >= NR_GIC_LOCAL_IRQS )
+ writeq_relaxed(affinity, (GICD + GICD_IROUTER + irq * 8));
+
+ /* Set priority */
+ if ( irq < NR_GIC_LOCAL_IRQS )
+ writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq);
+ else
+ writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
+
+ spin_unlock(&gicv3.lock);
+}
+
+static void __init gicv3_dist_init(void)
+{
+ uint32_t type;
+ uint32_t priority;
+ uint64_t affinity;
+ int i;
+
+ /* Disable the distributor */
+ writel_relaxed(0, GICD + GICD_CTLR);
+
+ type = readl_relaxed(GICD + GICD_TYPER);
+ gicv3_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
+
+ printk("GICv3: %d lines, (IID %8.8x).\n",
+ gicv3_info.nr_lines, readl_relaxed(GICD + GICD_IIDR));
+
+ /* Default all global IRQs to level, active low */
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 16 )
+ writel_relaxed(0, GICD + GICD_ICFGR + (i / 16) * 4);
+
+ /* Default priority for global interrupts */
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 4 )
+ {
+ priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ);
+ writel_relaxed(priority, GICD + GICD_IPRIORITYR + (i / 4) * 4);
+ }
+
+ /* Disable all global interrupts */
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 32 )
+ writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4);
+
+ gicv3_dist_wait_for_rwp();
+
+ /* Turn on the distributor */
+ writel_relaxed(GICD_CTL_ENABLE | GICD_CTLR_ARE_NS |
+ GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR);
+
+ /* Route all global IRQs to this CPU */
+ affinity = gicv3_mpidr_to_affinity(smp_processor_id());
+ /* Make sure we don't broadcast the interrupt */
+ affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
+
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i++ )
+ writeq_relaxed(affinity, GICD + GICD_IROUTER + i * 8);
+}
+
+static int gicv3_enable_redist(void)
+{
+ uint32_t val;
+ bool_t timeout = 0;
+ s_time_t deadline = NOW() + MILLISECS(1000);
+
+ /* Wake up this CPU redistributor */
+ val = readl_relaxed(GICD_RDIST_BASE + GICR_WAKER);
+ val &= ~GICR_WAKER_ProcessorSleep;
+ writel_relaxed(val, GICD_RDIST_BASE + GICR_WAKER);
+
+ do {
+ val = readl_relaxed(GICD_RDIST_BASE + GICR_WAKER);
+ if ( !(val & GICR_WAKER_ChildrenAsleep) )
+ break;
+ if ( NOW() > deadline )
+ {
+ timeout = 1;
+ break;
+ }
+ cpu_relax();
+ udelay(1);
+ } while ( timeout );
+
+ if ( timeout )
+ {
+ dprintk(XENLOG_ERR, "GICv3: Redist enable RWP timeout\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static int __init gicv3_populate_rdist(void)
+{
+ int i;
+ uint32_t aff;
+ uint32_t reg;
+ uint64_t typer;
+ uint64_t mpidr = cpu_logical_map(smp_processor_id());
+
+ /*
+ * Convert affinity to a 32bit value that can be matched to GICR_TYPER
+ * bits [63:32]
+ */
+ aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ void __iomem *ptr = gicv3.rdist_regions[i].map_base;
+
+ reg = readl_relaxed(ptr + GICR_PIDR2) & GICR_PIDR2_ARCH_MASK;
+ if ( reg != GICV3_GICR_PIDR2_ARCH )
+ {
+ dprintk(XENLOG_ERR,
+ "GICv3: No redistributor present @%"PRIpaddr"\n",
+ gicv3.rdist_regions[i].base);
+ break;
+ }
+
+ do {
+ typer = readq_relaxed(ptr + GICR_TYPER);
+
+ if ( (typer >> 32) == aff )
+ {
+ this_cpu(rbase) = ptr;
+ printk("GICv3: CPU%d: Found redistributor in region %d @%p\n",
+ smp_processor_id(), i, ptr);
+ return 0;
+ }
+ if ( gicv3.rdist_stride )
+ ptr += gicv3.rdist_stride;
+ else
+ {
+ ptr += SZ_64K * 2;
+ if ( typer & GICR_TYPER_VLPIS )
+ ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
+ }
+
+ } while ( !(typer & GICR_TYPER_LAST) );
+ }
+
+ dprintk(XENLOG_ERR, "GICv3: CPU%d: mpidr 0x%x has no re-distributor!\n",
+ smp_processor_id(), cpu_logical_map(smp_processor_id()));
+ return -ENODEV;
+}
+
+static int __cpuinit gicv3_cpu_init(void)
+{
+ int i;
+ uint32_t priority;
+
+ /* Register ourselves with the rest of the world */
+ if ( gicv3_populate_rdist() )
+ return -ENODEV;
+
+ if ( gicv3_enable_redist() )
+ return -ENODEV;
+
+ /* Set priority on PPI and SGI interrupts */
+ priority = (GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 | GIC_PRI_IPI << 8 |
+ GIC_PRI_IPI);
+ for (i = 0; i < NR_GIC_SGI; i += 4)
+ writel_relaxed(priority,
+ GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + (i / 4) * 4);
+
+ priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 | GIC_PRI_IRQ << 8 |
+ GIC_PRI_IRQ);
+ for (i = NR_GIC_SGI; i < NR_GIC_LOCAL_IRQS; i += 4)
+ writel_relaxed(priority,
+ GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + (i / 4) * 4);
+
+ /*
+ * Disable all PPI interrupts, ensure all SGI interrupts are
+ * enabled.
+ */
+ writel_relaxed(0xffff0000, GICD_RDIST_SGI_BASE + GICR_ICENABLER0);
+ writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0);
+
+ gicv3_redist_wait_for_rwp();
+
+ /* Enable system registers */
+ gicv3_enable_sre();
+
+ /* No priority grouping */
+ WRITE_SYSREG32(0, ICC_BPR1_EL1);
+
+ /* Set priority mask register */
+ WRITE_SYSREG32(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
+
+ /* EOI drops priority too (mode 0) */
+ WRITE_SYSREG32(GICC_CTLR_EL1_EOImode_drop, ICC_CTLR_EL1);
+
+ /* Enable Group1 interrupts */
+ WRITE_SYSREG32(1, ICC_IGRPEN1_EL1);
+
+ /* Sync at once at the end of cpu interface configuration */
+ isb();
+
+ return 0;
+}
+
+static void gicv3_cpu_disable(void)
+{
+ WRITE_SYSREG32(0, ICC_CTLR_EL1);
+ isb();
+}
+
+static void __cpuinit gicv3_hyp_init(void)
+{
+ uint32_t vtr;
+
+ vtr = READ_SYSREG32(ICH_VTR_EL2);
+ gicv3_info.nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
+ gicv3.nr_priorities = ((vtr >> GICH_VTR_PRIBITS_SHIFT) &
+ GICH_VTR_PRIBITS_MASK) + 1;
+
+ if ( !((gicv3.nr_priorities > 4) && (gicv3.nr_priorities < 8)) )
+ panic("GICv3: Invalid number of priority bits\n");
+
+ WRITE_SYSREG32(GICH_VMCR_EOI | GICH_VMCR_VENG1, ICH_VMCR_EL2);
+ WRITE_SYSREG32(GICH_HCR_EN, ICH_HCR_EL2);
+}
+
+/* Set up the per-CPU parts of the GIC for a secondary CPU */
+static int gicv3_secondary_cpu_init(void)
+{
+ int res;
+
+ spin_lock(&gicv3.lock);
+
+ res = gicv3_cpu_init();
+ gicv3_hyp_init();
+
+ spin_unlock(&gicv3.lock);
+
+ return res;
+}
+
+static void __cpuinit gicv3_hyp_disable(void)
+{
+ uint32_t vtr;
+
+ vtr = READ_SYSREG32(ICH_HCR_EL2);
+ vtr &= ~0x1;
+ WRITE_SYSREG32(vtr, ICH_HCR_EL2);
+ isb();
+}
+
+static u16 gicv3_compute_target_list(int *base_cpu, const struct cpumask *mask,
+ uint64_t cluster_id)
+{
+ int cpu = *base_cpu;
+ uint64_t mpidr = cpu_logical_map(cpu);
+ u16 tlist = 0;
+
+ while ( cpu < nr_cpu_ids )
+ {
+ /*
+ * If we ever get a cluster of more than 16 CPUs, just
+ * scream and skip that CPU.
+ */
+ if ( (mpidr & 0xff) >= 16 )
+ {
+ dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
+ goto out;
+ }
+ tlist |= 1 << (mpidr & 0xf);
+
+ cpu = cpumask_next(cpu, mask);
+ if ( cpu == nr_cpu_ids )
+ {
+ cpu--;
+ goto out;
+ }
+
+ mpidr = cpu_logical_map(cpu);
+ if ( cluster_id != (mpidr & ~0xffUL) ) {
+ cpu--;
+ goto out;
+ }
+ }
+out:
+ *base_cpu = cpu;
+
+ return tlist;
+}
+
+static void gicv3_send_sgi(enum gic_sgi sgi, enum gic_sgi_mode mode,
+ const cpumask_t *cpumask)
+{
+ int cpu = 0;
+ uint64_t val;
+
+ for_each_cpu(cpu, cpumask)
+ {
+ /* Mask lower 8 bits. It represent cpu in affinity level 0 */
+ uint64_t cluster_id = cpu_logical_map(cpu) & ~0xffUL;
+ u16 tlist;
+
+ /* Get targetlist for the cluster to send SGI */
+ tlist = gicv3_compute_target_list(&cpu, cpumask, cluster_id);
+
+ /*
+ * Prepare affinity path of the cluster for which SGI is generated
+ * along with SGI number
+ */
+ val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 |
+ MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 |
+ sgi << 24 |
+ MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 |
+ tlist);
+
+ WRITE_SYSREG(val, ICC_SGI1R_EL1);
+ }
+ /* Force above writes to ICC_SGI1R_EL1 */
+ isb();
+}
+
+/* Shut down the per-CPU GIC interface */
+static void gicv3_disable_interface(void)
+{
+ spin_lock(&gicv3.lock);
+
+ gicv3_cpu_disable();
+ gicv3_hyp_disable();
+
+ spin_unlock(&gicv3.lock);
+}
+
+static void gicv3_update_lr(int lr, const struct pending_irq *p,
+ unsigned int state)
+{
+ uint64_t grp = GICH_LR_GRP1;
+ uint64_t val = 0;
+
+ BUG_ON(lr >= gicv3_info.nr_lrs);
+ BUG_ON(lr < 0);
+
+ val = (((uint64_t)state & 0x3) << GICH_LR_STATE_SHIFT) | grp;
+ val |= ((uint64_t)p->priority & 0xff) << GICH_LR_PRIORITY_SHIFT;
+ val |= ((uint64_t)p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT;
+
+ if ( p->desc != NULL )
+ val |= GICH_LR_HW | (((uint64_t)p->desc->irq & GICH_LR_PHYSICAL_MASK)
+ << GICH_LR_PHYSICAL_SHIFT);
+
+ gicv3_ich_write_lr(lr, val);
+}
+
+static void gicv3_clear_lr(int lr)
+{
+ gicv3_ich_write_lr(lr, 0);
+}
+
+static void gicv3_read_lr(int lr, struct gic_lr *lr_reg)
+{
+ uint64_t lrv;
+
+ lrv = gicv3_ich_read_lr(lr);
+
+ lr_reg->pirq = (lrv >> GICH_LR_PHYSICAL_SHIFT) & GICH_LR_PHYSICAL_MASK;
+ lr_reg->virq = (lrv >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
+
+ lr_reg->priority = (lrv >> GICH_LR_PRIORITY_SHIFT) & GICH_LR_PRIORITY_MASK;
+ lr_reg->state = (lrv >> GICH_LR_STATE_SHIFT) & GICH_LR_STATE_MASK;
+ lr_reg->hw_status = (lrv >> GICH_LR_HW_SHIFT) & GICH_LR_HW_MASK;
+ lr_reg->grp = (lrv >> GICH_LR_GRP_SHIFT) & GICH_LR_GRP_MASK;
+}
+
+static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
+{
+ uint64_t lrv = 0;
+
+ lrv = ( ((u64)(lr->pirq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT)|
+ ((u64)(lr->virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT) |
+ ((u64)(lr->priority & GICH_LR_PRIORITY_MASK) << GICH_LR_PRIORITY_SHIFT)|
+ ((u64)(lr->state & GICH_LR_STATE_MASK) << GICH_LR_STATE_SHIFT) |
+ ((u64)(lr->hw_status & GICH_LR_HW_MASK) << GICH_LR_HW_SHIFT) |
+ ((u64)(lr->grp & GICH_LR_GRP_MASK) << GICH_LR_GRP_SHIFT) );
+
+ gicv3_ich_write_lr(lr_reg, lrv);
+}
+
+static int gicv_v3_init(struct domain *d)
+{
+ int i;
+
+ /*
+ * Domain 0 gets the hardware address.
+ * Guests get the virtual platform layout.
+ */
+ if ( is_hardware_domain(d) )
+ {
+ d->arch.vgic.dbase = gicv3.dbase;
+ d->arch.vgic.dbase_size = gicv3.dbase_size;
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ d->arch.vgic.rbase[i] = gicv3.rdist_regions[i].base;
+ d->arch.vgic.rbase_size[i] = gicv3.rdist_regions[i].size;
+ }
+ d->arch.vgic.rdist_stride = gicv3.rdist_stride;
+ d->arch.vgic.rdist_count = gicv3.rdist_count;
+ }
+ else
+ d->arch.vgic.dbase = GUEST_GICD_BASE;
+
+ d->arch.vgic.nr_lines = 0;
+
+ return 0;
+}
+
+static void gicv3_hcr_status(uint32_t flag, bool_t status)
+{
+ uint32_t hcr;
+
+ hcr = READ_SYSREG32(ICH_HCR_EL2);
+ if ( status )
+ WRITE_SYSREG32(hcr | flag, ICH_HCR_EL2);
+ else
+ WRITE_SYSREG32(hcr & (~flag), ICH_HCR_EL2);
+ isb();
+}
+
+static unsigned int gicv3_read_vmcr_priority(void)
+{
+ return ((READ_SYSREG32(ICH_VMCR_EL2) >> GICH_VMCR_PRIORITY_SHIFT) &
+ GICH_VMCR_PRIORITY_MASK);
+}
+
+/* Only support reading GRP1 APRn registers */
+static unsigned int gicv3_read_apr(int apr_reg)
+{
+ switch ( apr_reg )
+ {
+ case 0:
+ ASSERT(gicv3.nr_priorities > 4 && gicv3.nr_priorities < 8);
+ return READ_SYSREG32(ICH_AP1R0_EL2);
+ case 1:
+ ASSERT(gicv3.nr_priorities > 5 && gicv3.nr_priorities < 8);
+ return READ_SYSREG32(ICH_AP1R1_EL2);
+ case 2:
+ ASSERT(gicv3.nr_priorities > 6 && gicv3.nr_priorities < 8);
+ return READ_SYSREG32(ICH_AP1R2_EL2);
+ default:
+ BUG();
+ }
+}
+
+static void gicv3_irq_enable(struct irq_desc *desc)
+{
+ unsigned long flags;
+
+ ASSERT(spin_is_locked(&desc->lock));
+
+ spin_lock_irqsave(&gicv3.lock, flags);
+ desc->status &= ~IRQ_DISABLED;
+ dsb(sy);
+ /* Enable routing */
+ gicv3_unmask_irq(desc);
+ spin_unlock_irqrestore(&gicv3.lock, flags);
+}
+
+static void gicv3_irq_disable(struct irq_desc *desc)
+{
+ unsigned long flags;
+
+ ASSERT(spin_is_locked(&desc->lock));
+
+ spin_lock_irqsave(&gicv3.lock, flags);
+ /* Disable routing */
+ gicv3_mask_irq(desc);
+ desc->status |= IRQ_DISABLED;
+ spin_unlock_irqrestore(&gicv3.lock, flags);
+}
+
+static unsigned int gicv3_irq_startup(struct irq_desc *desc)
+{
+ gicv3_irq_enable(desc);
+
+ return 0;
+}
+
+static void gicv3_irq_shutdown(struct irq_desc *desc)
+{
+ gicv3_irq_disable(desc);
+}
+
+static void gicv3_irq_ack(struct irq_desc *desc)
+{
+ /* No ACK -- reading IAR has done this for us */
+}
+
+static void gicv3_host_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority */
+ gicv3_eoi_irq(desc);
+ /* Deactivate */
+ gicv3_dir_irq(desc);
+}
+
+static void gicv3_guest_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority of the IRQ */
+ gicv3_eoi_irq(desc);
+ /* Deactivation happens in maintenance interrupt / via GICV */
+}
+
+static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
+{
+ BUG();
+}
+
+static const hw_irq_controller gicv3_host_irq_type = {
+ .typename = "gic-v3",
+ .startup = gicv3_irq_startup,
+ .shutdown = gicv3_irq_shutdown,
+ .enable = gicv3_irq_enable,
+ .disable = gicv3_irq_disable,
+ .ack = gicv3_irq_ack,
+ .end = gicv3_host_irq_end,
+ .set_affinity = gicv3_irq_set_affinity,
+};
+
+static const hw_irq_controller gicv3_guest_irq_type = {
+ .typename = "gic-v3",
+ .startup = gicv3_irq_startup,
+ .shutdown = gicv3_irq_shutdown,
+ .enable = gicv3_irq_enable,
+ .disable = gicv3_irq_disable,
+ .ack = gicv3_irq_ack,
+ .end = gicv3_guest_irq_end,
+ .set_affinity = gicv3_irq_set_affinity,
+};
+
+static const struct gic_hw_operations gicv3_ops = {
+ .info = &gicv3_info,
+ .save_state = gicv3_save_state,
+ .restore_state = gicv3_restore_state,
+ .dump_state = gicv3_dump_state,
+ .gicv_setup = gicv_v3_init,
+ .gic_host_irq_type = &gicv3_host_irq_type,
+ .gic_guest_irq_type = &gicv3_guest_irq_type,
+ .eoi_irq = gicv3_eoi_irq,
+ .deactivate_irq = gicv3_dir_irq,
+ .read_irq = gicv3_read_irq,
+ .set_irq_properties = gicv3_set_irq_properties,
+ .send_SGI = gicv3_send_sgi,
+ .disable_interface = gicv3_disable_interface,
+ .update_lr = gicv3_update_lr,
+ .update_hcr_status = gicv3_hcr_status,
+ .clear_lr = gicv3_clear_lr,
+ .read_lr = gicv3_read_lr,
+ .write_lr = gicv3_write_lr,
+ .read_vmcr_priority = gicv3_read_vmcr_priority,
+ .read_apr = gicv3_read_apr,
+ .secondary_init = gicv3_secondary_cpu_init,
+};
+
+/* Set up the GIC */
+static int __init gicv3_init(struct dt_device_node *node, const void *data)
+{
+ struct rdist_region *rdist_regs;
+ int res, i;
+ uint32_t reg;
+
+ dt_device_set_used_by(node, DOMID_XEN);
+
+ res = dt_device_get_address(node, 0, &gicv3.dbase, &gicv3.dbase_size);
+ if ( res || !gicv3.dbase )
+ panic("GICv3: Cannot find a valid distributor address");
+
+ if ( (gicv3.dbase & ~PAGE_MASK) || (gicv3.dbase_size & ~PAGE_MASK) )
+ panic("GICv3: Found unaligned distributor address %"PRIpaddr"",
+ gicv3.dbase);
+
+ gicv3.map_dbase = ioremap_nocache(gicv3.dbase, gicv3.dbase_size);
+ if ( !gicv3.map_dbase )
+ panic("GICv3: Failed to ioremap for GIC distributor\n");
+
+ reg = readl_relaxed(GICD + GICD_PIDR2) & GICD_PIDR2_ARCH_MASK;
+ if ( reg != GICV3_GICD_PIDR2_ARCH )
+ panic("GICv3: no distributor detected\n");
+
+ if ( !dt_property_read_u32(node, "#redistributor-regions",
+ &gicv3.rdist_count) )
+ gicv3.rdist_count = 1;
+
+ if ( gicv3.rdist_count > MAX_RDIST_COUNT )
+ panic("GICv3: Number of redistributor regions is more than"
+ "%d (Increase MAX_RDIST_COUNT!!)\n", MAX_RDIST_COUNT);
+
+ rdist_regs = xzalloc_array(struct rdist_region, gicv3.rdist_count);
+ if ( !rdist_regs )
+ panic("GICv3: Failed to allocate memory for rdist regions\n");
+
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ uint64_t rdist_base, rdist_size;
+
+ res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size);
+ if ( res || !rdist_base )
+ panic("GICv3: No rdist base found for region %d\n", i);
+
+ rdist_regs[i].base = rdist_base;
+ rdist_regs[i].size = rdist_size;
+ }
+
+ /* If stride is not set in dt. Set default to 2 * SZ_64K */
+ if ( !dt_property_read_u32(node, "redistributor-stride", &gicv3.rdist_stride) )
+ gicv3.rdist_stride = 0;
+
+ gicv3.rdist_regions= rdist_regs;
+
+ res = platform_get_irq(node, 0);
+ if ( res < 0 )
+ panic("GICv3: Cannot find the maintenance IRQ");
+ gicv3_info.maintenance_irq = res;
+
+ /* Set the GIC as the primary interrupt controller */
+ dt_interrupt_controller = node;
+
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ /* map dbase & rdist regions */
+ gicv3.rdist_regions[i].map_base =
+ ioremap_nocache(gicv3.rdist_regions[i].base,
+ gicv3.rdist_regions[i].size);
+
+ if ( !gicv3.rdist_regions[i].map_base )
+ panic("GICv3: Failed to ioremap rdist region for region %d\n", i);
+ }
+
+ printk("GICv3 initialization:\n"
+ " gic_dist_addr=%"PRIpaddr"\n"
+ " gic_dist_size=%"PRIpaddr"\n"
+ " gic_dist_mapaddr=%p\n"
+ " gic_rdist_regions=%d\n"
+ " gic_rdist_stride=%x\n"
+ " gic_rdist_base=%"PRIpaddr"\n"
+ " gic_rdist_base_size=%"PRIpaddr"\n"
+ " gic_rdist_base_mapaddr=%p\n"
+ " gic_maintenance_irq=%u\n",
+ gicv3.dbase, gicv3.dbase_size, gicv3.map_dbase, gicv3.rdist_count,
+ gicv3.rdist_stride, gicv3.rdist_regions[0].base,
+ gicv3.rdist_regions[0].size, gicv3.rdist_regions[0].map_base,
+ gicv3_info.maintenance_irq);
+
+ spin_lock_init(&gicv3.lock);
+
+ spin_lock(&gicv3.lock);
+
+ gicv3_dist_init();
+ res = gicv3_cpu_init();
+ gicv3_hyp_init();
+
+ gicv3_info.hw_version = GIC_V3;
+ /* Register hw ops*/
+ register_gic_ops(&gicv3_ops);
+
+ spin_unlock(&gicv3.lock);
+
+ return res;
+}
+
+static const char * const gicv3_dt_compat[] __initconst =
+{
+ DT_MATCH_GIC_V3_STRING1,
+ NULL
+};
+
+DT_DEVICE_START(gicv3, "GICv3", DEVICE_GIC)
+ .compatible = gicv3_dt_compat,
+ .init = gicv3_init,
+DT_DEVICE_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 32d0554..787e93c 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -99,6 +99,14 @@ struct arch_domain
/* Base address for guest GIC */
paddr_t dbase; /* Distributor base address */
paddr_t cbase; /* CPU base address */
+#ifdef CONFIG_ARM_64
+ /* GIC V3 addressing */
+ paddr_t dbase_size; /* Distributor base size */
+ paddr_t rbase[MAX_RDIST_COUNT]; /* Re-Distributor base address */
+ paddr_t rbase_size[MAX_RDIST_COUNT]; /* Re-Distributor size */
+ uint32_t rdist_stride; /* Re-Distributor stride */
+ int rdist_count; /* No. of Re-Distributors */
+#endif
} vgic;
struct vuart {
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index a0c07bf..d5a2fcf 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -18,6 +18,10 @@
#ifndef __ASM_ARM_GIC_H__
#define __ASM_ARM_GIC_H__
+#define NR_GIC_LOCAL_IRQS NR_LOCAL_IRQS
+#define NR_GIC_SGI 16
+#define MAX_RDIST_COUNT 4
+
#define GICD_CTLR (0x000)
#define GICD_TYPER (0x004)
#define GICD_IIDR (0x008)
@@ -154,6 +158,20 @@
#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \
DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A7)
+#define DT_MATCH_GIC_V3_STRING1 "arm,gic-v3"
+
+#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V3_STRING1);
+
+/*
+ * GICv3 registers that needs to be saved/restored
+ */
+struct gic_v3 {
+ uint32_t hcr, vmcr, sre_el1;
+ uint32_t apr0[4];
+ uint32_t apr1[4];
+ uint64_t lr[16];
+};
+
/*
* GICv2 register that needs to be saved/restored
* on VCPU context switch
@@ -170,6 +188,7 @@ struct gic_v2 {
*/
union gic_state_data {
struct gic_v2 v2;
+ struct gic_v3 v3;
};
/*
@@ -189,6 +208,7 @@ struct gic_lr {
enum gic_version {
GIC_V2,
+ GIC_V3,
};
extern enum gic_version gic_hw_version(void);
diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
new file mode 100644
index 0000000..1c32e0c
--- /dev/null
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -0,0 +1,159 @@
+/*
+ * ARM Generic Interrupt Controller v3 definitions
+ *
+ * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>
+ * Copyright (c) 2014 Cavium Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_GIC_V3_DEFS_H__
+#define __ASM_ARM_GIC_V3_DEFS_H__
+
+/*
+ * Additional registers defined in GIC v3.
+ * Common GICD registers are defined in gic.h
+ */
+
+#define GICD_STATUSR (0x010)
+#define GICD_SETSPI_NSR (0x040)
+#define GICD_CLRSPI_NSR (0x048)
+#define GICD_SETSPI_SR (0x050)
+#define GICD_CLRSPI_SR (0x058)
+#define GICD_IROUTER (0x6000)
+#define GICD_IROUTER31 (0x60F8)
+#define GICD_IROUTER32 (0x6100)
+#define GICD_IROUTERN (0x7FF8)
+#define GICD_PIDR0 (0xFFE0)
+#define GICD_PIDR1 (0xFFE4)
+#define GICD_PIDR2 (0xFFE8)
+#define GICD_PIDR3 (0xFFEC)
+#define GICD_PIDR4 (0xFFD0)
+#define GICD_PIDR5 (0xFFD4)
+#define GICD_PIDR7 (0xFFDC)
+
+#define GICC_SRE_EL2_SRE (1UL << 0)
+#define GICC_SRE_EL2_DFB (1UL << 1)
+#define GICC_SRE_EL2_DIB (1UL << 2)
+#define GICC_SRE_EL2_ENEL1 (1UL << 3)
+
+#define GICD_CTLR_RWP (1UL << 31)
+#define GICD_CTLR_ARE_NS (1U << 4)
+#define GICD_CTLR_ENABLE_G1A (1U << 1)
+#define GICD_CTLR_ENABLE_G1 (1U << 0)
+#define GICD_IROUTER_SPI_MODE_ANY (1UL << 31)
+
+#define GICC_CTLR_EL1_EOImode_drop (1U << 1)
+
+#define GICR_WAKER_ProcessorSleep (1U << 1)
+#define GICR_WAKER_ChildrenAsleep (1U << 2)
+
+#define GICV3_GICD_PIDR0 (0x92)
+#define GICV3_GICD_PIDR1 (0xb4)
+#define GICV3_GICD_PIDR2_ARCH (0x30)
+#define GICV3_GICD_PIDR2 (0x3b)
+#define GICV3_GICD_PIDR4 (0x04)
+#define GICD_PIDR2_ARCH_MASK (0xf0)
+
+#define GICV3_GICR_PIDR0 (0x93)
+#define GICV3_GICR_PIDR1 GICV3_GICD_PIDR1
+#define GICV3_GICR_PIDR2_ARCH GICV3_GICD_PIDR2_ARCH
+#define GICV3_GICR_PIDR2 GICV3_GICD_PIDR2
+#define GICV3_GICR_PIDR4 GICV3_GICD_PIDR4
+#define GICR_PIDR2_ARCH_MASK GICD_PIDR2_ARCH_MASK
+#define GICR_SYNCR_NOT_BUSY 1
+/*
+ * Implementation defined value JEP106?
+ * use physical hw value for now
+ */
+#define GICV3_GICD_IIDR_VAL 0x34c
+#define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL
+
+#define GICR_CTLR (0x0000)
+#define GICR_IIDR (0x0004)
+#define GICR_TYPER (0x0008)
+#define GICR_STATUSR (0x0010)
+#define GICR_WAKER (0x0014)
+#define GICR_SETLPIR (0x0040)
+#define GICR_CLRLPIR (0x0048)
+#define GICR_PROPBASER (0x0070)
+#define GICR_PENDBASER (0x0078)
+#define GICR_INVLPIR (0x00A0)
+#define GICR_INVALLR (0x00B0)
+#define GICR_SYNCR (0x00C0)
+#define GICR_MOVLPIR (0x100)
+#define GICR_MOVALLR (0x0110)
+#define GICR_PIDR0 GICD_PIDR0
+#define GICR_PIDR1 GICD_PIDR1
+#define GICR_PIDR2 GICD_PIDR2
+#define GICR_PIDR3 GICD_PIDR3
+#define GICR_PIDR4 GICD_PIDR4
+#define GICR_PIDR5 GICD_PIDR5
+#define GICR_PIDR7 GICD_PIDR7
+
+/* GICR for SGI's & PPI's */
+
+#define GICR_IGROUPR0 (0x0080)
+#define GICR_IGRPMODR0 (0x0F80)
+#define GICR_ISENABLER0 (0x0100)
+#define GICR_ICENABLER0 (0x0180)
+#define GICR_ISPENDR0 (0x0200)
+#define GICR_ICPENDR0 (0x0280)
+#define GICR_ISACTIVER0 (0x0300)
+#define GICR_ICACTIVER0 (0x0380)
+#define GICR_IPRIORITYR0 (0x0400)
+#define GICR_IPRIORITYR7 (0x041C)
+#define GICR_ICFGR0 (0x0C00)
+#define GICR_ICFGR1 (0x0C04)
+#define GICR_NSACR (0x0E00)
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_LAST (1U << 4)
+
+#define DEFAULT_PMR_VALUE 0xff
+
+#define GICH_VMCR_EOI (1 << 9)
+#define GICH_VMCR_VENG1 (1 << 1)
+
+#define GICH_LR_VIRTUAL_MASK 0xffff
+#define GICH_LR_VIRTUAL_SHIFT 0
+#define GICH_LR_PHYSICAL_MASK 0x3ff
+#define GICH_LR_PHYSICAL_SHIFT 32
+#define GICH_LR_STATE_MASK 0x3
+#define GICH_LR_STATE_SHIFT 62
+#define GICH_LR_PRIORITY_MASK 0xff
+#define GICH_LR_PRIORITY_SHIFT 48
+#define GICH_LR_HW_MASK 0x1
+#define GICH_LR_HW_SHIFT 61
+#define GICH_LR_GRP_MASK 0x1
+#define GICH_LR_GRP_SHIFT 60
+#define GICH_LR_MAINTENANCE_IRQ (1UL<<41)
+#define GICH_LR_GRP1 (1UL<<60)
+#define GICH_LR_HW (1UL<<61)
+
+#define GICH_VTR_NRLRGS 0x3f
+#define GICH_VTR_PRIBITS_MASK 0x7
+#define GICH_VTR_PRIBITS_SHIFT 29
+
+#define GICH_VMCR_PRIORITY_MASK 0xff
+#define GICH_VMCR_PRIORITY_SHIFT 24
+
+#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index bdfff4e..ccaa9da 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -17,6 +17,20 @@
#define MPIDR_HWID_MASK _AC(0xffffff,U)
#define MPIDR_INVALID (~MPIDR_HWID_MASK)
+/*
+ * Macros to extract affinity level. picked from kernel
+ */
+
+#define MPIDR_LEVEL_BITS_SHIFT 3
+#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
+#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+
+#define MPIDR_LEVEL_SHIFT(level) \
+ (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
+
+#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
+ ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
+
/* TTBCR Translation Table Base Control Register */
#define TTBCR_EAE _AC(0x80000000,U)
#define TTBCR_N_MASK _AC(0x07,U)
diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
index e81b80e..7aef378 100644
--- a/xen/include/xen/lib.h
+++ b/xen/include/xen/lib.h
@@ -67,6 +67,8 @@ do { \
#define reserve_bootmem(_p,_l) ((void)0)
+#define SZ_64K 0x00010000
+
struct domain;
void cmdline_parse(const char *cmdline);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v7 2/5] xen/arm: Add virtual GICv3 support
2014-07-11 12:51 [PATCH v7 0/5] xen/arm: Add GICv3 support vijay.kilari
2014-07-11 12:51 ` [PATCH v7 1/5] xen/arm: Add support for GIC v3 vijay.kilari
@ 2014-07-11 12:51 ` vijay.kilari
2014-07-14 15:59 ` Julien Grall
2014-07-16 11:47 ` Ian Campbell
2014-07-11 12:51 ` [PATCH v7 3/5] xen/arm: Update Dom0 GIC dt node with GICv3 information vijay.kilari
` (3 subsequent siblings)
5 siblings, 2 replies; 38+ messages in thread
From: vijay.kilari @ 2014-07-11 12:51 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, manish.jaggi, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Add virtual GICv3 driver support.
Also, with this patch vgic_irq_rank structure is modified to
hold GICv2 GICD_TARGET and GICv3 GICD_ROUTER registers under
union.
This patch adds only basic GICv3 support.
Does not support Interrupt Translation support (ITS)
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
v7: Fixed coding style.
v6: Removed byte read access for IROUTERN register.
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/vgic-v2.c | 8 +-
xen/arch/arm/vgic-v3.c | 902 ++++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic.c | 5 +
xen/include/asm-arm/vgic.h | 13 +-
5 files changed, 924 insertions(+), 5 deletions(-)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 1684c09..ba61e58 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -28,6 +28,7 @@ obj-y += smp.o
obj-y += shutdown.o
obj-y += traps.o
obj-y += vgic.o vgic-v2.o
+obj-$(CONFIG_ARM_64) += vgic-v3.o
obj-y += vtimer.o
obj-y += vuart.o
obj-y += hvm.o
diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
index 2102e43..d65146a 100644
--- a/xen/arch/arm/vgic-v2.c
+++ b/xen/arch/arm/vgic-v2.c
@@ -133,7 +133,7 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ *r = rank->v2.itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
DABT_WORD)];
if ( dabt.size == DABT_BYTE )
*r = vgic_byte_read(*r, dabt.sign, gicd_reg);
@@ -361,10 +361,10 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
if ( dabt.size == DABT_WORD )
- rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ rank->v2.itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
DABT_WORD)] = *r;
else
- vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
+ vgic_byte_write(&rank->v2.itargets[REG_RANK_INDEX(8,
gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -466,7 +466,7 @@ static int vgic_v2_vcpu_init(struct vcpu *v)
/* For SGI and PPI the target is always this CPU */
for ( i = 0 ; i < 8 ; i++ )
- v->arch.vgic.private_irqs->itargets[i] =
+ v->arch.vgic.private_irqs->v2.itargets[i] =
(1<<(v->vcpu_id+0))
| (1<<(v->vcpu_id+8))
| (1<<(v->vcpu_id+16))
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
new file mode 100644
index 0000000..2bf0e7c
--- /dev/null
+++ b/xen/arch/arm/vgic-v3.c
@@ -0,0 +1,902 @@
+/*
+ * xen/arch/arm/vgic-v3.c
+ *
+ * ARM Virtual Generic Interrupt Controller v3 support
+ * based on xen/arch/arm/vgic.c
+ *
+ * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>
+ * Copyright (c) 2014 Cavium Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/bitops.h>
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/softirq.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+
+#include <asm/current.h>
+#include <asm/device.h>
+
+#include <asm/mmio.h>
+#include <asm/gic_v3_defs.h>
+#include <asm/gic.h>
+#include <asm/vgic.h>
+
+static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ uint64_t aff;
+
+ switch ( gicr_reg )
+ {
+ case GICR_CTLR:
+ /* We have not implemented LPI's, read zero */
+ goto read_as_zero;
+ case GICR_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_IIDR_VAL;
+ return 1;
+ case GICR_TYPER:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ /* TBD: Update processor id in [23:8] when ITS support is added */
+ aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32);
+ *r = aff;
+ return 1;
+ case GICR_STATUSR:
+ /* Not implemented */
+ goto read_as_zero;
+ case GICR_WAKER:
+ /* Power management is not implemented */
+ goto read_as_zero;
+ case GICR_SETLPIR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ case GICR_CLRLPIR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ case GICR_PROPBASER:
+ /* LPI's not implemented */
+ goto read_as_zero_64;
+ case GICR_PENDBASER:
+ /* LPI's not implemented */
+ goto read_as_zero_64;
+ case GICR_INVLPIR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ case GICR_INVALLR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ return 0;
+ case GICR_SYNCR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* RO . But when read it always returns busy bito bit[0] */
+ *r = GICR_SYNCR_NOT_BUSY;
+ return 1;
+ case GICR_MOVLPIR:
+ /* WO Read as zero */
+ goto read_as_zero_64;
+ case GICR_MOVALLR:
+ /* WO Read as zero */
+ goto read_as_zero_64;
+ case GICR_PIDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR0;
+ return 1;
+ case GICR_PIDR1:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR1;
+ return 1;
+ case GICR_PIDR2:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR2;
+ return 1;
+ case GICR_PIDR3:
+ /* Manufacture/customer defined */
+ goto read_as_zero;
+ case GICR_PIDR4:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR4;
+ return 1;
+ case GICR_PIDR5 ... GICR_PIDR7:
+ /* Reserved0 */
+ goto read_as_zero;
+ default:
+ printk("vGICv3: vGICR: read r%d offset %#08x\n not found",
+ dabt.reg, gicr_reg);
+ return 0;
+ }
+bad_width:
+ printk("vGICv3: vGICR: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+
+ switch ( gicr_reg )
+ {
+ case GICR_CTLR:
+ /* LPI's not implemented */
+ goto write_ignore;
+ case GICR_IIDR:
+ /* RO */
+ goto write_ignore;
+ case GICR_TYPER:
+ /* RO */
+ goto write_ignore_64;
+ case GICR_STATUSR:
+ /* Not implemented */
+ goto write_ignore;
+ case GICR_WAKER:
+ /* Power mgmt not implemented */
+ goto write_ignore;
+ case GICR_SETLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_CLRLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_PROPBASER:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_PENDBASER:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_INVLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_INVALLR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_SYNCR:
+ /* RO */
+ goto write_ignore;
+ case GICR_MOVLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_MOVALLR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_PIDR7... GICR_PIDR0:
+ /* RO */
+ goto write_ignore;
+ default:
+ printk("vGICR: write r%d offset %#08x\n not found", dabt.reg, gicr_reg);
+ return 0;
+ }
+bad_width:
+ printk("vGICR: bad write width %d r%d=%"PRIregister" offset %#08x\n",
+ dabt.size, dabt.reg, *r, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ return 1;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+static int __vgic_v3_distr_common_mmio_read(struct vcpu *v, mmio_info_t *info,
+ uint32_t reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+
+ switch ( reg )
+ {
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ISPENDR, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ICPENDR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+
+ vgic_lock_rank(v, rank);
+ *r = rank->ipriority[REG_RANK_INDEX(8, reg - GICD_IPRIORITYR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
+ *r = vgic_byte_read(*r, dabt.sign, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICFGR ... GICD_ICFGRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)];
+ vgic_unlock_rank(v, rank);
+ return 1;
+ default:
+ printk("GICv3: vGICD/vGICR: unhandled read r%d offset %#08x\n",
+ dabt.reg, reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "vGICv3: vGICD/vGICR: bad read width %d r%d \
+ offset %#08x\n", dabt.size, dabt.reg, reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int __vgic_v3_distr_common_mmio_write(struct vcpu *v, mmio_info_t *info,
+ uint32_t reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ uint32_t tr;
+
+ switch ( reg )
+ {
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable |= *r;
+ vgic_unlock_rank(v, rank);
+ /* The irq number is extracted from offset. so shift by register size */
+ vgic_enable_irqs(v, (*r) & (~tr), (reg - GICD_ISENABLER) >> DABT_WORD);
+ return 1;
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable &= ~*r;
+ vgic_unlock_rank(v, rank);
+ /* The irq number is extracted from offset. so shift by register size */
+ vgic_disable_irqs(v, (*r) & tr, (reg - GICD_ICENABLER) >> DABT_WORD);
+ return 1;
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ISPENDR, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->ipend = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ICPENDR, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->ipend &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ if ( dabt.size == DABT_WORD )
+ rank->ipriority[REG_RANK_INDEX(8, reg - GICD_IPRIORITYR,
+ DABT_WORD)] = *r;
+ else
+ vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
+ reg - GICD_IPRIORITYR, DABT_WORD)], *r, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICFGR: /* Restricted to configure SGIs */
+ goto write_ignore;
+ case GICD_ICFGR + 4 ... GICD_ICFGRN: /* PPI + SPIs */
+ /* ICFGR1 for PPI's, which is implementation defined
+ if ICFGR1 is programmable or not. We chose to program */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)] = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ default:
+ printk("vGICv3: vGICD/vGICR: unhandled write r%d \
+ =%"PRIregister" offset %#08x\n", dabt.reg, *r, reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "vGICv3: vGICD/vGICR: bad write width %d \
+ r%d=%"PRIregister" offset %#08x\n", dabt.size, dabt.reg, *r, reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+static int vgic_v3_rdistr_sgi_mmio_read(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+
+ switch ( gicr_reg )
+ {
+ case GICR_IGRPMODR0:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+ case GICR_IGROUPR0:
+ case GICR_ISENABLER0:
+ case GICR_ICENABLER0:
+ case GICR_ISACTIVER0:
+ case GICR_ICACTIVER0:
+ case GICR_IPRIORITYR0...GICR_IPRIORITYR7:
+ case GICR_ICFGR0... GICR_ICFGR1:
+ /*
+ * Above registers offset are common with GICD.
+ * So handle in common with GICD handling
+ */
+ return __vgic_v3_distr_common_mmio_read(v, info, gicr_reg);
+ case GICR_ISPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicr_reg - GICR_ISPENDR0, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->pendsgi;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_ICPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicr_reg - GICR_ICPENDR0, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->pendsgi;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_NSACR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+ default:
+ printk("vGICv3: vGICR: read r%d offset %#08x\n not found",
+ dabt.reg, gicr_reg);
+ return 0;
+ }
+bad_width:
+ printk("vGICv3: vGICR: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int vgic_v3_rdistr_sgi_mmio_write(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+
+ switch ( gicr_reg )
+ {
+ case GICR_IGRPMODR0:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ case GICR_IGROUPR0:
+ case GICR_ISENABLER0:
+ case GICR_ICENABLER0:
+ case GICR_ISACTIVER0:
+ case GICR_ICACTIVER0:
+ case GICR_ICFGR1:
+ case GICR_IPRIORITYR0...GICR_IPRIORITYR7:
+ /*
+ * Above registers offset are common with GICD.
+ * So handle common with GICD handling
+ */
+ return __vgic_v3_distr_common_mmio_write(v, info, gicr_reg);
+ case GICR_ISPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicr_reg - GICR_ISACTIVER0, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ /* TODO: we just store the SGI pending status. Handle it properly */
+ rank->pendsgi |= *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_ICPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicr_reg - GICR_ISACTIVER0, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ /* TODO: we just store the SGI pending status. Handle it properly */
+ rank->pendsgi &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_NSACR:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ default:
+ printk("vGICv3: vGICR SGI: write r%d offset %#08x\n not found",
+ dabt.reg, gicr_reg);
+ return 0;
+ }
+
+bad_width:
+ printk("vGICR SGI: bad write width %d r%d=%"PRIregister" offset %#08x\n",
+ dabt.size, dabt.reg, *r, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+static int vgic_v3_rdistr_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ uint32_t offset;
+
+ offset = info->gpa & (v->domain->arch.vgic.rdist_stride - 1);
+
+ if ( offset < SZ_64K )
+ return __vgic_v3_rdistr_rd_mmio_read(v, info, offset);
+ else if ( (offset >= SZ_64K) && (offset < 2 * SZ_64K) )
+ return vgic_v3_rdistr_sgi_mmio_read(v, info, (offset - SZ_64K));
+ else
+ gdprintk(XENLOG_WARNING, "vGICv3: vGICR: unknown gpa read address \
+ %"PRIpaddr"\n", info->gpa);
+
+ return 0;
+}
+
+static int vgic_v3_rdistr_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ uint32_t offset;
+
+ offset = info->gpa & (v->domain->arch.vgic.rdist_stride - 1);
+ if ( offset < SZ_64K )
+ return __vgic_v3_rdistr_rd_mmio_write(v, info, offset);
+ else if ( (offset >= SZ_64K) && (offset < 2 * SZ_64K) )
+ return vgic_v3_rdistr_sgi_mmio_write(v, info, (offset - SZ_64K));
+ else
+ gdprintk(XENLOG_WARNING, "vGICV3: vGICR: unknown gpa write address \
+ %"PRIpaddr"\n", info->gpa);
+
+ return 0;
+}
+
+static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vgic_lock(v);
+ *r = v->domain->arch.vgic.ctlr;
+ vgic_unlock(v);
+ return 1;
+ case GICD_TYPER:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* No secure world support for guests. */
+ *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) |
+ ((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES));
+ return 1;
+ case GICD_STATUSR:
+ /*
+ * Optional, Not implemented for now.
+ * Update to support guest debugging.
+ */
+ goto read_as_zero;
+ case GICD_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_IIDR_VAL;
+ return 1;
+ case 0x020 ... 0x03c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- read as zero */
+ goto read_as_zero;
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ case GICD_ICFGR ... GICD_ICFGRN:
+ /*
+ * Above all register are common with GICR and GICD
+ * Manage in common
+ */
+ return __vgic_v3_distr_common_mmio_read(v, info, gicd_reg);
+ case GICD_IROUTER ... GICD_IROUTER31:
+ /* SGI/PPI is RES0 */
+ goto read_as_zero_64;
+ case GICD_IROUTER32 ... GICD_IROUTERN:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER, DABT_DOUBLE_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ /* IROUTER is 64 bit so, to make it byte size right shift by 3.
+ Here once. macro REG_RANK_INDEX will do it twice */
+ *r = rank->v3.irouter[REG_RANK_INDEX(64,
+ (gicd_reg - GICD_IROUTER), DABT_DOUBLE_WORD)];
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+ case GICD_SGIR:
+ /* Read as ICH_SGIR system register with SRE set. So ignore */
+ goto read_as_zero;
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ /* Replaced with GICR_ICPENDR0. So ignore write */
+ goto read_as_zero;
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ /* Replaced with GICR_ISPENDR0. So ignore write */
+ goto read_as_zero;
+ case GICD_PIDR0:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR0;
+ return 1;
+ case GICD_PIDR1:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR1;
+ return 1;
+ case GICD_PIDR2:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR2;
+ return 1;
+ case GICD_PIDR3:
+ /* GICv3 identification value. Manufacturer/Customer defined */
+ goto read_as_zero;
+ case GICD_PIDR4:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR4;
+ return 1;
+ case GICD_PIDR5 ... GICD_PIDR7:
+ /* Reserved0 */
+ goto read_as_zero;
+ case 0x00c:
+ case 0x044:
+ case 0x04c:
+ case 0x05c ... 0x07c:
+ case 0xf30 ... 0x5fcc:
+ case 0x8000 ... 0xbfcc:
+ /* These are reserved register addresses */
+ printk("vGICv3: vGICD: read unknown 0x00c .. 0xfcc r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ goto read_as_zero;
+ default:
+ printk("vGICv3: vGICD: unhandled read r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "vGICv3: vGICD: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* Ignore all but the enable bit */
+ v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
+ return 1;
+ case GICD_TYPER:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GICD_IIDR:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GICD_STATUSR:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GICD_SETSPI_NSR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case GICD_CLRSPI_NSR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case GICD_SETSPI_SR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case GICD_CLRSPI_SR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case 0x020 ... 0x03c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- write ignored */
+ printk("vGICD: write unknown 0x020 - 0x03c r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ goto write_ignore;
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ case GICD_ICFGR ... GICD_ICFGRN:
+ /* Above registers are common with GICR and GICD
+ * Manage in common */
+ return __vgic_v3_distr_common_mmio_write(v, info, gicd_reg);
+ case GICD_IROUTER ... GICD_IROUTER31:
+ /* SGI/PPI is RES0 */
+ goto write_ignore_64;
+ case GICD_IROUTER32 ... GICD_IROUTERN:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER, DABT_DOUBLE_WORD);
+ if ( rank == NULL) goto write_ignore_64;
+ if ( *r )
+ {
+ /* TODO: Ignored. We don't support irq delivery for vcpu != 0 */
+ gdprintk(XENLOG_DEBUG,
+ "SPI delivery to secondary cpus not supported\n");
+ goto write_ignore_64;
+ }
+ vgic_lock_rank(v, rank);
+ rank->v3.irouter[REG_RANK_INDEX(64,
+ (gicd_reg - GICD_IROUTER), DABT_DOUBLE_WORD)] = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ case GICD_SGIR:
+ /* it is accessed as system register in GICv3 */
+ goto write_ignore;
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ /* Replaced with GICR_ICPENDR0. So ignore write */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 0;
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ /* Replaced with GICR_ISPENDR0. So ignore write */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 0;
+ case GICD_PIDR7... GICD_PIDR0:
+ /* RO -- write ignore */
+ goto write_ignore;
+ case 0x00c:
+ case 0x044:
+ case 0x04c:
+ case 0x05c ... 0x07c:
+ case 0xf30 ... 0x5fcc:
+ case 0x8000 ... 0xbfcc:
+ /* Reserved register addresses */
+ printk("vGICv3: vGICD: write unknown 0x00c 0xfcc r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ goto write_ignore;
+ default:
+ printk("vGICv3: vGICD: unhandled write r%d=%"PRIregister" \
+ offset %#08x\n", dabt.reg, *r, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "VGICv3: vGICD: bad write width %d r%d=%"PRIregister" \
+ offset %#08x\n", dabt.size, dabt.reg, *r, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+
+write_ignore_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ return 1;
+}
+
+static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
+ .read_handler = vgic_v3_rdistr_mmio_read,
+ .write_handler = vgic_v3_rdistr_mmio_write,
+};
+
+static const struct mmio_handler_ops vgic_distr_mmio_handler = {
+ .read_handler = vgic_v3_distr_mmio_read,
+ .write_handler = vgic_v3_distr_mmio_write,
+};
+
+static int vgicv3_vcpu_init(struct vcpu *v)
+{
+ int i;
+ uint64_t affinity;
+
+ /* For SGI and PPI the target is always this CPU */
+ affinity = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 32 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 16 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 8 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0));
+
+ for ( i = 0 ; i < 32 ; i++ )
+ v->arch.vgic.private_irqs->v3.irouter[i] = affinity;
+
+ return 0;
+}
+
+static int vgicv3_domain_init(struct domain *d)
+{
+ int i;
+
+ /* We rely on gicv init to get dbase and size */
+ register_mmio_handler(d, &vgic_distr_mmio_handler, d->arch.vgic.dbase,
+ d->arch.vgic.dbase_size);
+
+ /*
+ * Register mmio handler per redistributor region but not for
+ * every sgi rdist region which is per core.
+ * The redistributor region encompasses per core sgi region.
+ */
+ for ( i = 0; i < d->arch.vgic.rdist_count; i++ )
+ register_mmio_handler(d, &vgic_rdistr_mmio_handler,
+ d->arch.vgic.rbase[i], d->arch.vgic.rbase_size[i]);
+
+ return 0;
+}
+
+static const struct vgic_ops v3_ops = {
+ .vcpu_init = vgicv3_vcpu_init,
+ .domain_init = vgicv3_domain_init,
+};
+
+int vgic_v3_init(struct domain *d)
+{
+ register_vgic_ops(d, &v3_ops);
+ return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index d223db4..3647497 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -69,6 +69,11 @@ int domain_vgic_init(struct domain *d)
switch ( gic_hw_version() )
{
+#ifdef CONFIG_ARM_64
+ case GIC_V3:
+ vgic_v3_init(d);
+ break;
+#endif
case GIC_V2:
if ( vgic_v2_init(d) )
return -ENODEV;
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 19eed7e..f580b78 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -83,7 +83,14 @@ struct vgic_irq_rank {
uint32_t ienable, iactive, ipend, pendsgi;
uint32_t icfg[2];
uint32_t ipriority[8];
- uint32_t itargets[8];
+ union {
+ struct {
+ uint32_t itargets[8];
+ }v2;
+ struct {
+ uint64_t irouter[32];
+ }v3;
+ };
};
struct vgic_ops {
@@ -110,6 +117,9 @@ static inline int REG_RANK_NR(int b, uint32_t n)
{
switch ( b )
{
+ case 64: return n >> 6;
+ case 32: return n >> 5;
+ case 16: return n >> 4;
case 8: return n >> 3;
case 4: return n >> 2;
case 2: return n >> 1;
@@ -159,6 +169,7 @@ extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
int vgic_v2_init(struct domain *d);
+int vgic_v3_init(struct domain *d);
extern int vcpu_vgic_free(struct vcpu *v);
extern int vgic_to_sgi(struct vcpu *v, register_t sgir,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v7 3/5] xen/arm: Update Dom0 GIC dt node with GICv3 information
2014-07-11 12:51 [PATCH v7 0/5] xen/arm: Add GICv3 support vijay.kilari
2014-07-11 12:51 ` [PATCH v7 1/5] xen/arm: Add support for GIC v3 vijay.kilari
2014-07-11 12:51 ` [PATCH v7 2/5] xen/arm: Add virtual GICv3 support vijay.kilari
@ 2014-07-11 12:51 ` vijay.kilari
2014-07-16 11:53 ` Ian Campbell
2014-07-11 12:51 ` [PATCH v7 4/5] xen/arm: add SGI handling for GICv3 vijay.kilari
` (2 subsequent siblings)
5 siblings, 1 reply; 38+ messages in thread
From: vijay.kilari @ 2014-07-11 12:51 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, manish.jaggi, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Update GIC device tree node for DOM0 with GICv3
information. GIC hw specfic device tree information
is moved to respective GIC driver.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
---
xen/arch/arm/domain_build.c | 47 ++-----------------------
xen/arch/arm/gic-v2.c | 51 +++++++++++++++++++++++++++
xen/arch/arm/gic-v3.c | 80 ++++++++++++++++++++++++++++++++++++++++++-
xen/arch/arm/gic.c | 6 ++++
xen/include/asm-arm/gic.h | 8 +++--
5 files changed, 144 insertions(+), 48 deletions(-)
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 8c850ca..40e83f3 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -526,9 +526,6 @@ static int make_gic_node(const struct domain *d, void *fdt,
const struct dt_device_node *node)
{
const struct dt_device_node *gic = dt_interrupt_controller;
- const void *compatible = NULL;
- u32 len;
- __be32 *new_cells, *tmp;
int res = 0;
/*
@@ -543,48 +540,7 @@ static int make_gic_node(const struct domain *d, void *fdt,
DPRINT("Create gic node\n");
- compatible = dt_get_property(gic, "compatible", &len);
- if ( !compatible )
- {
- dprintk(XENLOG_ERR, "Can't find compatible property for the gic node\n");
- return -FDT_ERR_XEN(ENOENT);
- }
-
- res = fdt_begin_node(fdt, "interrupt-controller");
- if ( res )
- return res;
-
- res = fdt_property(fdt, "compatible", compatible, len);
- if ( res )
- return res;
-
- res = fdt_property_cell(fdt, "#interrupt-cells", 3);
- if ( res )
- return res;
-
- res = fdt_property(fdt, "interrupt-controller", NULL, 0);
-
- if ( res )
- return res;
-
- len = dt_cells_to_size(dt_n_addr_cells(node) + dt_n_size_cells(node));
- len *= 2; /* GIC has two memory regions: Distributor + CPU interface */
- new_cells = xzalloc_bytes(len);
- if ( new_cells == NULL )
- return -FDT_ERR_XEN(ENOMEM);
-
- tmp = new_cells;
- DPRINT(" Set Distributor Base 0x%"PRIpaddr"-0x%"PRIpaddr"\n",
- d->arch.vgic.dbase, d->arch.vgic.dbase + PAGE_SIZE - 1);
- dt_set_range(&tmp, node, d->arch.vgic.dbase, PAGE_SIZE);
-
- DPRINT(" Set Cpu Base 0x%"PRIpaddr"-0x%"PRIpaddr"\n",
- d->arch.vgic.cbase, d->arch.vgic.cbase + (PAGE_SIZE * 2) - 1);
- dt_set_range(&tmp, node, d->arch.vgic.cbase, PAGE_SIZE * 2);
-
- res = fdt_property(fdt, "reg", new_cells, len);
- xfree(new_cells);
-
+ res = gic_make_node(d, node, fdt);
if ( res )
return res;
@@ -805,6 +761,7 @@ static int handle_node(struct domain *d, struct kernel_info *kinfo,
static const struct dt_device_match gic_matches[] __initconst =
{
DT_MATCH_GIC_V2,
+ DT_MATCH_GIC_V3,
{ /* sentinel */ },
};
static const struct dt_device_match timer_matches[] __initconst =
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index cc60af8..c1b9abe 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -27,6 +27,7 @@
#include <xen/softirq.h>
#include <xen/list.h>
#include <xen/device_tree.h>
+#include <xen/libfdt/libfdt.h>
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
@@ -537,6 +538,55 @@ static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
BUG();
}
+static int gicv2_make_dt_node(const struct domain *d,
+ const struct dt_device_node *node, void *fdt)
+{
+ const struct dt_device_node *gic = dt_interrupt_controller;
+ const void *compatible = NULL;
+ u32 len;
+ __be32 *new_cells, *tmp;
+ int res = 0;
+
+ compatible = dt_get_property(gic, "compatible", &len);
+ if ( !compatible )
+ {
+ dprintk(XENLOG_ERR, "Can't find compatible property for the gic node\n");
+ return -FDT_ERR_XEN(ENOENT);
+ }
+
+ res = fdt_begin_node(fdt, "interrupt-controller");
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "compatible", compatible, len);
+ if ( res )
+ return res;
+
+ res = fdt_property_cell(fdt, "#interrupt-cells", 3);
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "interrupt-controller", NULL, 0);
+
+ if ( res )
+ return res;
+
+ len = dt_cells_to_size(dt_n_addr_cells(node) + dt_n_size_cells(node));
+ len *= 2; /* GIC has two memory regions: Distributor + CPU interface */
+ new_cells = xzalloc_bytes(len);
+ if ( new_cells == NULL )
+ return -FDT_ERR_XEN(ENOMEM);
+
+ tmp = new_cells;
+ dt_set_range(&tmp, node, d->arch.vgic.dbase, PAGE_SIZE);
+ dt_set_range(&tmp, node, d->arch.vgic.cbase, PAGE_SIZE * 2);
+
+ res = fdt_property(fdt, "reg", new_cells, len);
+ xfree(new_cells);
+
+ return res;
+}
+
/* XXX different for level vs edge */
static hw_irq_controller gicv2_host_irq_type = {
.typename = "gic-v2",
@@ -582,6 +632,7 @@ const static struct gic_hw_operations gicv2_ops = {
.write_lr = gicv2_write_lr,
.read_vmcr_priority = gicv2_read_vmcr_priority,
.read_apr = gicv2_read_apr,
+ .make_dt_node = gicv2_make_dt_node,
};
/* Set up the GIC */
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 473dd88..5ec5305 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -31,6 +31,7 @@
#include <xen/errno.h>
#include <xen/delay.h>
#include <xen/device_tree.h>
+#include <xen/libfdt/libfdt.h>
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/io.h>
@@ -1004,6 +1005,82 @@ static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
BUG();
}
+static int gicv3_make_dt_node(const struct domain *d,
+ const struct dt_device_node *node, void *fdt)
+{
+ const struct dt_device_node *gic = dt_interrupt_controller;
+ const void *compatible = NULL;
+ uint32_t len;
+ __be32 *new_cells, *tmp;
+ uint32_t rd_stride = 0;
+ uint32_t rd_count = 0;
+
+ int i, res = 0;
+
+ compatible = dt_get_property(gic, "compatible", &len);
+ if ( !compatible )
+ {
+ dprintk(XENLOG_ERR, "Can't find compatible property for the gic node\n");
+ return -FDT_ERR_XEN(ENOENT);
+ }
+
+ res = fdt_begin_node(fdt, "interrupt-controller");
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "compatible", compatible, len);
+ if ( res )
+ return res;
+
+ res = fdt_property_cell(fdt, "#interrupt-cells", 3);
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "interrupt-controller", NULL, 0);
+ if ( res )
+ return res;
+
+ res = dt_property_read_u32(gic, "redistributor-stride", &rd_stride);
+ if ( !res )
+ rd_stride = 0;
+
+ res = dt_property_read_u32(gic, "#redistributor-regions", &rd_count);
+ if ( !res )
+ rd_count = 1;
+
+ res = fdt_property_cell(fdt, "redistributor-stride", rd_stride);
+ if ( res )
+ return res;
+
+ res = fdt_property_cell(fdt, "#redistributor-regions", rd_count);
+ if ( res )
+ return res;
+
+ len = dt_cells_to_size(dt_n_addr_cells(node) + dt_n_size_cells(node));
+ /*
+ * GIC has two memory regions: Distributor + rdist regions
+ * CPU interface and virtual cpu interfaces accessesed as System registers
+ * So cells are created only for Distributor and rdist regions
+ */
+ len = len * (d->arch.vgic.rdist_count + 1);
+ new_cells = xzalloc_bytes(len);
+ if ( new_cells == NULL )
+ return -FDT_ERR_XEN(ENOMEM);
+
+ tmp = new_cells;
+
+ dt_set_range(&tmp, node, d->arch.vgic.dbase, d->arch.vgic.dbase_size);
+
+ for ( i = 0; i < d->arch.vgic.rdist_count; i++ )
+ dt_set_range(&tmp, node, d->arch.vgic.rbase[i],
+ d->arch.vgic.rbase_size[i]);
+
+ res = fdt_property(fdt, "reg", new_cells, len);
+ xfree(new_cells);
+
+ return res;
+}
+
static const hw_irq_controller gicv3_host_irq_type = {
.typename = "gic-v3",
.startup = gicv3_irq_startup,
@@ -1048,6 +1125,7 @@ static const struct gic_hw_operations gicv3_ops = {
.read_vmcr_priority = gicv3_read_vmcr_priority,
.read_apr = gicv3_read_apr,
.secondary_init = gicv3_secondary_cpu_init,
+ .make_dt_node = gicv3_make_dt_node,
};
/* Set up the GIC */
@@ -1158,7 +1236,7 @@ static int __init gicv3_init(struct dt_device_node *node, const void *data)
static const char * const gicv3_dt_compat[] __initconst =
{
- DT_MATCH_GIC_V3_STRING1,
+ DT_COMPAT_GIC_V3,
NULL
};
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index c0d70b8..38aa7b5 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -616,6 +616,12 @@ void __cpuinit init_maintenance_interrupt(void)
"irq-maintenance", NULL);
}
+int gic_make_node(const struct domain *d,const struct dt_device_node *node,
+ void *fdt)
+{
+ return gic_hw_ops->make_dt_node(d, node, fdt);
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index d5a2fcf..51a0a26 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -158,9 +158,9 @@
#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \
DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A7)
-#define DT_MATCH_GIC_V3_STRING1 "arm,gic-v3"
+#define DT_COMPAT_GIC_V3 "arm,gic-v3"
-#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V3_STRING1);
+#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_V3)
/*
* GICv3 registers that needs to be saved/restored
@@ -336,9 +336,13 @@ struct gic_hw_operations {
unsigned int (*read_apr)(int apr_reg);
/* Secondary CPU init */
int (*secondary_init)(void);
+ int (*make_dt_node)(const struct domain *d,
+ const struct dt_device_node *node, void *fdt);
};
void register_gic_ops(const struct gic_hw_operations *ops);
+int gic_make_node(const struct domain *d,const struct dt_device_node *node,
+ void *fdt);
#endif /* __ASSEMBLY__ */
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-11 12:51 [PATCH v7 0/5] xen/arm: Add GICv3 support vijay.kilari
` (2 preceding siblings ...)
2014-07-11 12:51 ` [PATCH v7 3/5] xen/arm: Update Dom0 GIC dt node with GICv3 information vijay.kilari
@ 2014-07-11 12:51 ` vijay.kilari
2014-07-11 13:43 ` Julien Grall
2014-07-22 13:48 ` Stefano Stabellini
2014-07-11 12:51 ` [PATCH v7 5/5] xen/arm: check for GICv3 platform support vijay.kilari
2014-07-16 10:35 ` [PATCH v7 0/5] xen/arm: Add GICv3 support Ian Campbell
5 siblings, 2 replies; 38+ messages in thread
From: vijay.kilari @ 2014-07-11 12:51 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, manish.jaggi, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
Handle the trap and inject SGI to vcpu.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
v7: - Introduced callback for sysreg emulation
- Removed unused parameter in inject_undef_exception()
- Use inject_undef64_exception for reporting sysreg
handling failure
v6: - Removed forward declaration of vgic_to_sgi() in vgic-v3.c
- Used vgic callback for SGI handling
- Alignment changes
---
xen/arch/arm/traps.c | 15 +++++++++++
xen/arch/arm/vgic-v3.c | 52 +++++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic.c | 7 +++++
xen/include/asm-arm/gic_v3_defs.h | 7 +++++
xen/include/asm-arm/sysregs.h | 3 +++
xen/include/asm-arm/vgic.h | 3 +++
6 files changed, 87 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 686d8b7..775bef1 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -41,6 +41,7 @@
#include "decode.h"
#include "vtimer.h"
#include <asm/gic.h>
+#include <asm/vgic.h>
/* The base of the stack must always be double-word aligned, which means
* that both the kernel half of struct cpu_user_regs (which is pushed in
@@ -1641,6 +1642,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
domain_crash_synchronous();
}
break;
+ case HSR_SYSREG_ICC_SGI1R_EL1:
+ if ( !vgic_emulate(regs, hsr) )
+ {
+ dprintk(XENLOG_WARNING,
+ "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
+ inject_undef64_exception(regs, hsr.len);
+ }
+ break;
+ case HSR_SYSREG_ICC_SGI0R_EL1:
+ case HSR_SYSREG_ICC_ASGI1R_EL1:
+ /* TBD: Implement to support secure grp0/1 SGI forwarding */
+ dprintk(XENLOG_WARNING,
+ "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n");
+ inject_undef64_exception(regs, hsr.len);
default:
bad_sysreg:
{
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 2bf0e7c..feee486 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -834,6 +834,57 @@ write_ignore_64:
return 1;
}
+static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
+{
+ int virq;
+ int irqmode;
+ enum gic_sgi_mode sgi_mode;
+ unsigned long vcpu_mask = 0;
+
+ irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
+ virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
+ vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
+
+ /* Map GIC sgi value to enum value */
+ switch ( irqmode )
+ {
+ case ICH_SGI_TARGET_LIST:
+ sgi_mode = SGI_TARGET_LIST;
+ break;
+ case ICH_SGI_TARGET_OTHERS:
+ sgi_mode = SGI_TARGET_OTHERS;
+ break;
+ default:
+ BUG();
+ }
+
+ return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
+}
+
+static int vgicv3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr)
+{
+ struct vcpu *v = current;
+ struct hsr_sysreg sysreg = hsr.sysreg;
+ register_t *r = select_user_reg(regs, sysreg.reg);
+
+ ASSERT (hsr.ec == HSR_EC_SYSREG);
+
+ switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
+ {
+ case HSR_SYSREG_ICC_SGI1R_EL1:
+ /* WO */
+ if ( !sysreg.read )
+ return vgicv3_to_sgi(v, *r);
+ else
+ {
+ gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
+ return 0;
+ }
+ default:
+ return 0;
+ }
+}
+
static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
.read_handler = vgic_v3_rdistr_mmio_read,
.write_handler = vgic_v3_rdistr_mmio_write,
@@ -884,6 +935,7 @@ static int vgicv3_domain_init(struct domain *d)
static const struct vgic_ops v3_ops = {
.vcpu_init = vgicv3_vcpu_init,
.domain_init = vgicv3_domain_init,
+ .emulate_sysreg = vgicv3_emulate_sysreg,
};
int vgic_v3_init(struct domain *d)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 3647497..e15d509 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -343,6 +343,13 @@ out:
smp_send_event_check_mask(cpumask_of(v->processor));
}
+int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
+{
+ struct vcpu *v = current;
+
+ return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
index 1c32e0c..b94ba20 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -147,6 +147,13 @@
#define GICH_VMCR_PRIORITY_MASK 0xff
#define GICH_VMCR_PRIORITY_SHIFT 24
+#define ICH_SGI_IRQMODE_SHIFT 40
+#define ICH_SGI_IRQMODE_MASK 0x1
+#define ICH_SGI_TARGET_OTHERS 1
+#define ICH_SGI_TARGET_LIST 0
+#define ICH_SGI_IRQ_SHIFT 24
+#define ICH_SGI_IRQ_MASK 0xf
+#define ICH_SGI_TARGETLIST_MASK 0xffff
#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
/*
diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
index b00871c..48ea498 100644
--- a/xen/include/asm-arm/sysregs.h
+++ b/xen/include/asm-arm/sysregs.h
@@ -78,6 +78,9 @@
#define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2)
#define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0)
#define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0)
+#define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5)
+#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
+#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7)
#define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
#define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0)
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index f580b78..63ecfa1 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -98,6 +98,8 @@ struct vgic_ops {
int (*vcpu_init)(struct vcpu *v);
/* Domain specific initialization of vGIC */
int (*domain_init)(struct domain *d);
+ /* vGIC sysreg emulation */
+ int (*emulate_sysreg)(struct cpu_user_regs *regs, union hsr hsr);
};
/* Number of ranks of interrupt registers for a domain */
@@ -165,6 +167,7 @@ extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
extern void vgic_clear_pending_irqs(struct vcpu *v);
extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s);
+extern int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr);
extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v7 5/5] xen/arm: check for GICv3 platform support
2014-07-11 12:51 [PATCH v7 0/5] xen/arm: Add GICv3 support vijay.kilari
` (3 preceding siblings ...)
2014-07-11 12:51 ` [PATCH v7 4/5] xen/arm: add SGI handling for GICv3 vijay.kilari
@ 2014-07-11 12:51 ` vijay.kilari
2014-07-16 12:11 ` Ian Campbell
2014-07-16 10:35 ` [PATCH v7 0/5] xen/arm: Add GICv3 support Ian Campbell
5 siblings, 1 reply; 38+ messages in thread
From: vijay.kilari @ 2014-07-11 12:51 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, manish.jaggi, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
ID_AA64PFR0_EL1 register provides information about GIC support.
Check for this register in GICv3 driver.
Also print GICv3 support information in boot log
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
v7: - return -ENODEV on lack GICv3 platform support instead of
panic
---
xen/arch/arm/gic-v3.c | 7 +++++++
xen/arch/arm/setup.c | 5 +++--
xen/include/asm-arm/cpufeature.h | 1 +
xen/include/asm-arm/processor.h | 5 ++---
4 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 5ec5305..492fd54 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -38,6 +38,7 @@
#include <asm/device.h>
#include <asm/gic.h>
#include <asm/gic_v3_defs.h>
+#include <asm/cpufeature.h>
struct rdist_region {
paddr_t base;
@@ -1135,6 +1136,12 @@ static int __init gicv3_init(struct dt_device_node *node, const void *data)
int res, i;
uint32_t reg;
+ if ( !cpu_has_gicv3 )
+ {
+ dprintk(XENLOG_ERR, "Platform does not support GICv3\n");
+ return -ENODEV;
+ }
+
dt_device_set_used_by(node, DOMID_XEN);
res = dt_device_get_address(node, 0, &gicv3.dbase, &gicv3.dbase_size);
diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index 78dc7f5..6a90c81 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -100,9 +100,10 @@ static void __init processor_id(void)
cpu_has_el2_32 ? "64+32" : cpu_has_el2_64 ? "64" : "No",
cpu_has_el1_32 ? "64+32" : cpu_has_el1_64 ? "64" : "No",
cpu_has_el0_32 ? "64+32" : cpu_has_el0_64 ? "64" : "No");
- printk(" Extensions:%s%s\n",
+ printk(" Extensions:%s%s%s\n",
cpu_has_fp ? " FloatingPoint" : "",
- cpu_has_simd ? " AdvancedSIMD" : "");
+ cpu_has_simd ? " AdvancedSIMD" : "",
+ cpu_has_gicv3 ? " GICv3" : "");
printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]);
diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h
index 1d2c9c7..bd84c57 100644
--- a/xen/include/asm-arm/cpufeature.h
+++ b/xen/include/asm-arm/cpufeature.h
@@ -15,6 +15,7 @@
#define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1)
#define cpu_has_fp (boot_cpu_feature64(fp) == 0)
#define cpu_has_simd (boot_cpu_feature64(simd) == 0)
+#define cpu_has_gicv3 (boot_cpu_feature64(gicv3) == 1)
#endif
#define cpu_feature32(c, feat) ((c)->pfr32.feat)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index ccaa9da..0188800 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -188,9 +188,8 @@ struct cpuinfo_arm {
unsigned long el3:4;
unsigned long fp:4; /* Floating Point */
unsigned long simd:4; /* Advanced SIMD */
- unsigned long __res0:8;
-
- unsigned long __res1;
+ unsigned long gicv3:4; /* GIC support */
+ unsigned long __res0:36;
};
} pfr64;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-11 12:51 ` [PATCH v7 4/5] xen/arm: add SGI handling for GICv3 vijay.kilari
@ 2014-07-11 13:43 ` Julien Grall
2014-07-11 14:08 ` Ian Campbell
2014-07-22 13:48 ` Stefano Stabellini
1 sibling, 1 reply; 38+ messages in thread
From: Julien Grall @ 2014-07-11 13:43 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar, manish.jaggi
Hi Vijay,
On 07/11/2014 01:51 PM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
> Handle the trap and inject SGI to vcpu.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> ---
> v7: - Introduced callback for sysreg emulation
> - Removed unused parameter in inject_undef_exception()
> - Use inject_undef64_exception for reporting sysreg
> handling failure
>
> v6: - Removed forward declaration of vgic_to_sgi() in vgic-v3.c
> - Used vgic callback for SGI handling
> - Alignment changes
> ---
> xen/arch/arm/traps.c | 15 +++++++++++
> xen/arch/arm/vgic-v3.c | 52 +++++++++++++++++++++++++++++++++++++
> xen/arch/arm/vgic.c | 7 +++++
> xen/include/asm-arm/gic_v3_defs.h | 7 +++++
> xen/include/asm-arm/sysregs.h | 3 +++
> xen/include/asm-arm/vgic.h | 3 +++
> 6 files changed, 87 insertions(+)
>
> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> index 686d8b7..775bef1 100644
> --- a/xen/arch/arm/traps.c
> +++ b/xen/arch/arm/traps.c
> @@ -41,6 +41,7 @@
> #include "decode.h"
> #include "vtimer.h"
> #include <asm/gic.h>
> +#include <asm/vgic.h>
>
> /* The base of the stack must always be double-word aligned, which means
> * that both the kernel half of struct cpu_user_regs (which is pushed in
> @@ -1641,6 +1642,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
> domain_crash_synchronous();
> }
> break;
> + case HSR_SYSREG_ICC_SGI1R_EL1:
> + if ( !vgic_emulate(regs, hsr) )
> + {
> + dprintk(XENLOG_WARNING,
> + "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
> + inject_undef64_exception(regs, hsr.len);
> + }
> + break;
> + case HSR_SYSREG_ICC_SGI0R_EL1:
> + case HSR_SYSREG_ICC_ASGI1R_EL1:
> + /* TBD: Implement to support secure grp0/1 SGI forwarding */
> + dprintk(XENLOG_WARNING,
> + "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n");
> + inject_undef64_exception(regs, hsr.len);
> default:
> bad_sysreg:
> {
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 2bf0e7c..feee486 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -834,6 +834,57 @@ write_ignore_64:
> return 1;
> }
>
> +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
> +{
> + int virq;
> + int irqmode;
> + enum gic_sgi_mode sgi_mode;
> + unsigned long vcpu_mask = 0;
> +
> + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
> + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
> + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
> +
> + /* Map GIC sgi value to enum value */
> + switch ( irqmode )
> + {
> + case ICH_SGI_TARGET_LIST:
> + sgi_mode = SGI_TARGET_LIST;
> + break;
> + case ICH_SGI_TARGET_OTHERS:
> + sgi_mode = SGI_TARGET_OTHERS;
> + break;
> + default:
> + BUG();
> + }
> +
> + return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
> +}
> +
> +static int vgicv3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr)
> +{
> + struct vcpu *v = current;
> + struct hsr_sysreg sysreg = hsr.sysreg;
> + register_t *r = select_user_reg(regs, sysreg.reg);
> +
> + ASSERT (hsr.ec == HSR_EC_SYSREG);
> +
> + switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
> + {
> + case HSR_SYSREG_ICC_SGI1R_EL1:
> + /* WO */
> + if ( !sysreg.read )
> + return vgicv3_to_sgi(v, *r);
> + else
> + {
> + gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
> + return 0;
> + }
> + default:
> + return 0;
> + }
> +}
> +
> static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
> .read_handler = vgic_v3_rdistr_mmio_read,
> .write_handler = vgic_v3_rdistr_mmio_write,
> @@ -884,6 +935,7 @@ static int vgicv3_domain_init(struct domain *d)
> static const struct vgic_ops v3_ops = {
> .vcpu_init = vgicv3_vcpu_init,
> .domain_init = vgicv3_domain_init,
> + .emulate_sysreg = vgicv3_emulate_sysreg,
> };
>
> int vgic_v3_init(struct domain *d)
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 3647497..e15d509 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -343,6 +343,13 @@ out:
> smp_send_event_check_mask(cpumask_of(v->processor));
> }
>
> +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
> +{
> + struct vcpu *v = current;
> +
> + return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
> +}
> +
You didn't implement emulate_sysreg for vgic-v2. If the GICv3 is
misprogrammed, Xen will segfault...
Please either implement emulate_sysreg on vgic-v2 by return 1 or check
that the function is not NULL.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-11 13:43 ` Julien Grall
@ 2014-07-11 14:08 ` Ian Campbell
2014-07-11 14:12 ` Julien Grall
0 siblings, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-11 14:08 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 2014-07-11 at 14:43 +0100, Julien Grall wrote:
> > diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> > index 3647497..e15d509 100644
> > --- a/xen/arch/arm/vgic.c
> > +++ b/xen/arch/arm/vgic.c
> > @@ -343,6 +343,13 @@ out:
> > smp_send_event_check_mask(cpumask_of(v->processor));
> > }
> >
> > +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
> > +{
> > + struct vcpu *v = current;
> > +
> > + return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
> > +}
> > +
>
> You didn't implement emulate_sysreg for vgic-v2. If the GICv3 is
> misprogrammed, Xen will segfault...
Which isn't all that different to the BUG_ON(!->emulate_sysreg) which I
would be in favour of, since misprogramming the GIC is a coding error...
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-11 14:08 ` Ian Campbell
@ 2014-07-11 14:12 ` Julien Grall
2014-07-11 14:18 ` Ian Campbell
0 siblings, 1 reply; 38+ messages in thread
From: Julien Grall @ 2014-07-11 14:12 UTC (permalink / raw)
To: Ian Campbell
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini, manish.jaggi
On 07/11/2014 03:08 PM, Ian Campbell wrote:
> On Fri, 2014-07-11 at 14:43 +0100, Julien Grall wrote:
>>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>>> index 3647497..e15d509 100644
>>> --- a/xen/arch/arm/vgic.c
>>> +++ b/xen/arch/arm/vgic.c
>>> @@ -343,6 +343,13 @@ out:
>>> smp_send_event_check_mask(cpumask_of(v->processor));
>>> }
>>>
>>> +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
>>> +{
>>> + struct vcpu *v = current;
>>> +
>>> + return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
>>> +}
>>> +
>>
>> You didn't implement emulate_sysreg for vgic-v2. If the GICv3 is
>> misprogrammed, Xen will segfault...
>
> Which isn't all that different to the BUG_ON(!->emulate_sysreg) which I
> would be in favour of, since misprogramming the GIC is a coding error...
I expect this function to be called often (everytime the guest is
sending an SGI), so adding BUG_ON(!->emulate_sysreg) will "slow down"
the emulation.
Implementing the callback emulate_sysreg for vgic-v2 and adding BUG
inside would be another solution.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-11 14:12 ` Julien Grall
@ 2014-07-11 14:18 ` Ian Campbell
0 siblings, 0 replies; 38+ messages in thread
From: Ian Campbell @ 2014-07-11 14:18 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 2014-07-11 at 15:12 +0100, Julien Grall wrote:
> On 07/11/2014 03:08 PM, Ian Campbell wrote:
> > On Fri, 2014-07-11 at 14:43 +0100, Julien Grall wrote:
> >>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> >>> index 3647497..e15d509 100644
> >>> --- a/xen/arch/arm/vgic.c
> >>> +++ b/xen/arch/arm/vgic.c
> >>> @@ -343,6 +343,13 @@ out:
> >>> smp_send_event_check_mask(cpumask_of(v->processor));
> >>> }
> >>>
> >>> +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
> >>> +{
> >>> + struct vcpu *v = current;
> >>> +
> >>> + return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
> >>> +}
> >>> +
> >>
> >> You didn't implement emulate_sysreg for vgic-v2. If the GICv3 is
> >> misprogrammed, Xen will segfault...
> >
> > Which isn't all that different to the BUG_ON(!->emulate_sysreg) which I
> > would be in favour of, since misprogramming the GIC is a coding error...
>
> I expect this function to be called often (everytime the guest is
> sending an SGI), so adding BUG_ON(!->emulate_sysreg) will "slow down"
> the emulation.
Then use ASSERT which are in debug builds only.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 2/5] xen/arm: Add virtual GICv3 support
2014-07-11 12:51 ` [PATCH v7 2/5] xen/arm: Add virtual GICv3 support vijay.kilari
@ 2014-07-14 15:59 ` Julien Grall
2014-07-16 11:47 ` Ian Campbell
1 sibling, 0 replies; 38+ messages in thread
From: Julien Grall @ 2014-07-14 15:59 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar, manish.jaggi
Hi Vijay,
On 07/11/2014 01:51 PM, vijay.kilari@gmail.com wrote:
> +static int vgic_v3_rdistr_mmio_read(struct vcpu *v, mmio_info_t *info)
> +{
> + uint32_t offset;
> +
> + offset = info->gpa & (v->domain->arch.vgic.rdist_stride - 1);
> +
> + if ( offset < SZ_64K )
> + return __vgic_v3_rdistr_rd_mmio_read(v, info, offset);
> + else if ( (offset >= SZ_64K) && (offset < 2 * SZ_64K) )
> + return vgic_v3_rdistr_sgi_mmio_read(v, info, (offset - SZ_64K));
> + else
> + gdprintk(XENLOG_WARNING, "vGICv3: vGICR: unknown gpa read address \
> + %"PRIpaddr"\n", info->gpa);
I though I already said that on a previous version...
This is wrong, when you use
"foo\
base\n"
The compiler will concatenate the 2 strings without remove the tab/space
on the second one. So you will print smth like:
"foo base\n"
You have to use
"foo"
"base\n"
The remark is the same on various place within this file.
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index d223db4..3647497 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -69,6 +69,11 @@ int domain_vgic_init(struct domain *d)
>
> switch ( gic_hw_version() )
> {
> +#ifdef CONFIG_ARM_64
> + case GIC_V3:
> + vgic_v3_init(d);
You forgot to check the return value of vgic_v3_init.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 0/5] xen/arm: Add GICv3 support
2014-07-11 12:51 [PATCH v7 0/5] xen/arm: Add GICv3 support vijay.kilari
` (4 preceding siblings ...)
2014-07-11 12:51 ` [PATCH v7 5/5] xen/arm: check for GICv3 platform support vijay.kilari
@ 2014-07-16 10:35 ` Ian Campbell
2014-07-16 11:47 ` Vijay Kilari
5 siblings, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-16 10:35 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
> Add GICv3 support for arm64 platform.
I get lots of:
{standard input}:1476: Error: unknown or missing system register name at operand 1 -- `msr ICH_VMCR_EL2,x1'
I'm using:
$ aarch64-linux-gnu-gcc --version
aarch64-linux-gnu-gcc (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04) 4.8.3 20140401 (prerelease)
Do you have a pointer to a toolchain which can build this stuff?
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-11 12:51 ` [PATCH v7 1/5] xen/arm: Add support for GIC v3 vijay.kilari
@ 2014-07-16 11:41 ` Ian Campbell
2014-07-22 9:48 ` Vijay Kilari
0 siblings, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-16 11:41 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
> +static inline void gicv3_restore_lrs(int nr_lrs, const struct vcpu *v)
Other similar functions you have here use gicv3.nr_foo directly.
> + case 1:
> + WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2);
> + break;
Nit: whitespace.
> +static void gicv3_save_state(struct vcpu *v)
> +{
> +
> + /* No need for spinlocks here because interrupts are disabled around
> + * this call and it only accesses struct vcpu fields that cannot be
> + * accessed simultaneously by another pCPU.
> + *
> + * Make sure all stores to the GIC via the memory mapped interface
> + * are now visible to the system register interface
> + */
> + dsb(sy);
> + gicv3_save_lrs(gicv3_info.nr_lrs, v);
> + save_aprn_regs(&v->arch.gic);
> + v->arch.gic.v3.vmcr = READ_SYSREG32(ICH_VMCR_EL2);
> + v->arch.gic.v3.sre_el1 = READ_SYSREG32(ICC_SRE_EL1);
> +}
> +
> +static void gicv3_restore_state(const struct vcpu *v)
> +{
> + WRITE_SYSREG32(v->arch.gic.v3.sre_el1, ICC_SRE_EL1);
> + WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2);
> + restore_aprn_regs(&v->arch.gic);
> + gicv3_restore_lrs(gicv3_info.nr_lrs, v);
> +
> + /*
> + * Make sure all stores are visible the GIC
> + */
> + dsb(sy);
> +}
A reference to Section 4.8.17 of the GICv3 spec alongside these
functions would be very useful.
> +static void __cpuinit gicv3_hyp_disable(void)
> +{
> + uint32_t vtr;
> +
> + vtr = READ_SYSREG32(ICH_HCR_EL2);
> + vtr &= ~0x1;
Please can you add a define for this value, or reuse GICH_HCR_EN if
ICH_HCR_EL2 is compatible with GICv2 GICH_HCR.
Also calling the temporary vtr is confusing, ICH_VTR_EL2 is a different
register.
> +static u16 gicv3_compute_target_list(int *base_cpu, const struct cpumask *mask,
> + uint64_t cluster_id)
> +{
> + int cpu = *base_cpu;
> + uint64_t mpidr = cpu_logical_map(cpu);
> + u16 tlist = 0;
> +
> + while ( cpu < nr_cpu_ids )
> + {
> + /*
> + * If we ever get a cluster of more than 16 CPUs, just
> + * scream and skip that CPU.
> + */
> + if ( (mpidr & 0xff) >= 16 )
MPIPDR_EFF0_MASK if that's what this is, and at least once more in this
function.
> + {
> + dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
> + goto out;
Please validate this and complain in gicv3_init not every time we send
an SGI.
> +static void gicv3_send_sgi(enum gic_sgi sgi, enum gic_sgi_mode mode,
> + const cpumask_t *cpumask)
> +{
> + int cpu = 0;
> + uint64_t val;
> +
> + for_each_cpu(cpu, cpumask)
> + {
> + /* Mask lower 8 bits. It represent cpu in affinity level 0 */
> + uint64_t cluster_id = cpu_logical_map(cpu) & ~0xffUL;
Use MPIDR_AFF0_MASK not 0xff.
> diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
> new file mode 100644
> index 0000000..1c32e0c
> --- /dev/null
> +++ b/xen/include/asm-arm/gic_v3_defs.h
> +#ifndef __ASM_ARM_GIC_V3_DEFS_H__
> +#define __ASM_ARM_GIC_V3_DEFS_H__
> +
> +/*
> + * Additional registers defined in GIC v3.
> + * Common GICD registers are defined in gic.h
> + */
> +
> +#define GICD_STATUSR (0x010)
> [...][
> +#define GICV3_GICD_PIDR0 (0x92)
What is the distinction between variables with GIC[DR]_ prefixes and
those with GICV3_GIC[DR]_ ones?
> diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
> index e81b80e..7aef378 100644
> --- a/xen/include/xen/lib.h
> +++ b/xen/include/xen/lib.h
> @@ -67,6 +67,8 @@ do { \
>
> #define reserve_bootmem(_p,_l) ((void)0)
>
> +#define SZ_64K 0x00010000
This was already discussed in v6.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 0/5] xen/arm: Add GICv3 support
2014-07-16 10:35 ` [PATCH v7 0/5] xen/arm: Add GICv3 support Ian Campbell
@ 2014-07-16 11:47 ` Vijay Kilari
2014-07-16 12:38 ` Ian Campbell
0 siblings, 1 reply; 38+ messages in thread
From: Vijay Kilari @ 2014-07-16 11:47 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Wed, Jul 16, 2014 at 4:05 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
>> Add GICv3 support for arm64 platform.
>
> I get lots of:
> {standard input}:1476: Error: unknown or missing system register name at operand 1 -- `msr ICH_VMCR_EL2,x1'
>
> I'm using:
> $ aarch64-linux-gnu-gcc --version
> aarch64-linux-gnu-gcc (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04) 4.8.3 20140401 (prerelease)
>
> Do you have a pointer to a toolchain which can build this stuff?
I am using our internal toolchain based on GCC version 4.7
Regards
Vijay
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 2/5] xen/arm: Add virtual GICv3 support
2014-07-11 12:51 ` [PATCH v7 2/5] xen/arm: Add virtual GICv3 support vijay.kilari
2014-07-14 15:59 ` Julien Grall
@ 2014-07-16 11:47 ` Ian Campbell
2014-07-16 11:56 ` Vijay Kilari
1 sibling, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-16 11:47 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
Apart from the things Julien mentioned this looks good to me. One quick
question:
[...]
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index d223db4..3647497 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -69,6 +69,11 @@ int domain_vgic_init(struct domain *d)
>
> switch ( gic_hw_version() )
> {
> +#ifdef CONFIG_ARM_64
> + case GIC_V3:
> + vgic_v3_init(d);
> + break;
> +#endif
With the first patch applied we will run guests on GICv3 with GICv2
emulation. Is that expected to work (assuming suitable h/w support)?
My expectation was that this wasn't enabled by this series, which is
fine, I'm just wondering if it does just happen to work...
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 3/5] xen/arm: Update Dom0 GIC dt node with GICv3 information
2014-07-11 12:51 ` [PATCH v7 3/5] xen/arm: Update Dom0 GIC dt node with GICv3 information vijay.kilari
@ 2014-07-16 11:53 ` Ian Campbell
0 siblings, 0 replies; 38+ messages in thread
From: Ian Campbell @ 2014-07-16 11:53 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Update GIC device tree node for DOM0 with GICv3
> information. GIC hw specfic device tree information
> is moved to respective GIC driver.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
I think this patch represents a bisection hazard, since the previous
patch will have enabled gic v3 for dom0 but it is not described until
this patch is applied. I think that's a tricky one to resolve so I
propose we ignore it so long as systems with GICv2 work fine at each
step, which I think should be the case.
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index d5a2fcf..51a0a26 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -158,9 +158,9 @@
> #define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \
> DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A7)
>
> -#define DT_MATCH_GIC_V3_STRING1 "arm,gic-v3"
> +#define DT_COMPAT_GIC_V3 "arm,gic-v3"
>
> -#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V3_STRING1);
> +#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_V3)
Ideally you would fold these renamings into the earlier patch which
introduced these in the first place.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 2/5] xen/arm: Add virtual GICv3 support
2014-07-16 11:47 ` Ian Campbell
@ 2014-07-16 11:56 ` Vijay Kilari
0 siblings, 0 replies; 38+ messages in thread
From: Vijay Kilari @ 2014-07-16 11:56 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Wed, Jul 16, 2014 at 5:17 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
> Apart from the things Julien mentioned this looks good to me. One quick
> question:
>
> [...]
>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>> index d223db4..3647497 100644
>> --- a/xen/arch/arm/vgic.c
>> +++ b/xen/arch/arm/vgic.c
>> @@ -69,6 +69,11 @@ int domain_vgic_init(struct domain *d)
>>
>> switch ( gic_hw_version() )
>> {
>> +#ifdef CONFIG_ARM_64
>> + case GIC_V3:
>> + vgic_v3_init(d);
>> + break;
>> +#endif
>
> With the first patch applied we will run guests on GICv3 with GICv2
> emulation. Is that expected to work (assuming suitable h/w support)?
>
> My expectation was that this wasn't enabled by this series, which is
> fine, I'm just wondering if it does just happen to work...
Yes, this series does not support guests with GICv2. This was known
limitation.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 5/5] xen/arm: check for GICv3 platform support
2014-07-11 12:51 ` [PATCH v7 5/5] xen/arm: check for GICv3 platform support vijay.kilari
@ 2014-07-16 12:11 ` Ian Campbell
0 siblings, 0 replies; 38+ messages in thread
From: Ian Campbell @ 2014-07-16 12:11 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
This all looks good apart from:
> @@ -188,9 +188,8 @@ struct cpuinfo_arm {
> unsigned long el3:4;
> unsigned long fp:4; /* Floating Point */
> unsigned long simd:4; /* Advanced SIMD */
> - unsigned long __res0:8;
> -
> - unsigned long __res1;
> + unsigned long gicv3:4; /* GIC support */
> + unsigned long __res0:36;
Please leave __res1 alone. so:
unsigned long simd:4; /* Advanced SIMD */
- unsigned long __res0:8;
+ unsigned long __res0:4;
+ unsigned long gic:4; /* GIC support */
unsigned long __res1;
Also note that in the ARMv8 this field is just called "gic", so I have
done the same, please do it that way otherwise when gic vN adds a new
sysreg we'll just have to rename the field.
Ian
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 0/5] xen/arm: Add GICv3 support
2014-07-16 11:47 ` Vijay Kilari
@ 2014-07-16 12:38 ` Ian Campbell
2014-07-16 13:32 ` Ian Campbell
0 siblings, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-16 12:38 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Wed, 2014-07-16 at 17:17 +0530, Vijay Kilari wrote:
> On Wed, Jul 16, 2014 at 4:05 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> > On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
> >> Add GICv3 support for arm64 platform.
> >
> > I get lots of:
> > {standard input}:1476: Error: unknown or missing system register name at operand 1 -- `msr ICH_VMCR_EL2,x1'
> >
> > I'm using:
> > $ aarch64-linux-gnu-gcc --version
> > aarch64-linux-gnu-gcc (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04) 4.8.3 20140401 (prerelease)
> >
> > Do you have a pointer to a toolchain which can build this stuff?
>
> I am using our internal toolchain based on GCC version 4.7
OK. We really ought to find some publicly available toolchain before
accepting this code. Or else we need to make gic v3 functionality depend
on the toolstack, which would suck.
I'm going to see if the Linaro 4.9 gcc will do it.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 0/5] xen/arm: Add GICv3 support
2014-07-16 12:38 ` Ian Campbell
@ 2014-07-16 13:32 ` Ian Campbell
2014-07-23 10:51 ` Vijay Kilari
0 siblings, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-16 13:32 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Wed, 2014-07-16 at 13:38 +0100, Ian Campbell wrote:
> On Wed, 2014-07-16 at 17:17 +0530, Vijay Kilari wrote:
> > On Wed, Jul 16, 2014 at 4:05 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> > > On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
> > >> Add GICv3 support for arm64 platform.
> > >
> > > I get lots of:
> > > {standard input}:1476: Error: unknown or missing system register name at operand 1 -- `msr ICH_VMCR_EL2,x1'
> > >
> > > I'm using:
> > > $ aarch64-linux-gnu-gcc --version
> > > aarch64-linux-gnu-gcc (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04) 4.8.3 20140401 (prerelease)
> > >
> > > Do you have a pointer to a toolchain which can build this stuff?
> >
> > I am using our internal toolchain based on GCC version 4.7
>
> OK. We really ought to find some publicly available toolchain before
> accepting this code. Or else we need to make gic v3 functionality depend
> on the toolstack, which would suck.
>
> I'm going to see if the Linaro 4.9 gcc will do it.
Sadly not.
Mark Rutland pointed me to the workaround which Linux uses:
https://git.kernel.org/cgit/linux/kernel/git/maz/arm-platforms.git/tree/include/linux/irqchip/arm-gic-v3.h?h=gicv3/base&id=1545387f2ca2e51f5ccd3ed764348ee41e15c02f#n143
Which AFAICT works with at least Linaro's gcc 4.8 and 4.9. So I think
we'll have to go down this route.
Please could you make sure that this series compiles with the gcc from
either http://releases.linaro.org/14.04/components/toolchain/binaries
or
http://releases.linaro.org/14.06/components/toolchain/binaries
Presumably this will mostly be a case of adding the defines to
xen/include/asm-arm/sysregs.h.
Thanks,
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-16 11:41 ` Ian Campbell
@ 2014-07-22 9:48 ` Vijay Kilari
2014-07-22 10:01 ` Julien Grall
2014-07-22 10:39 ` Ian Campbell
0 siblings, 2 replies; 38+ messages in thread
From: Vijay Kilari @ 2014-07-22 9:48 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Wed, Jul 16, 2014 at 5:11 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
>> +static inline void gicv3_restore_lrs(int nr_lrs, const struct vcpu *v)
>> +static u16 gicv3_compute_target_list(int *base_cpu, const struct cpumask *mask,
>> + uint64_t cluster_id)
>> +{
>> + int cpu = *base_cpu;
>> + uint64_t mpidr = cpu_logical_map(cpu);
>> + u16 tlist = 0;
>> +
>> + while ( cpu < nr_cpu_ids )
>> + {
>> + /*
>> + * If we ever get a cluster of more than 16 CPUs, just
>> + * scream and skip that CPU.
>> + */
>> + if ( (mpidr & 0xff) >= 16 )
>
> MPIPDR_EFF0_MASK if that's what this is, and at least once more in this
> function.
>
>> + {
>> + dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
>> + goto out;
>
> Please validate this and complain in gicv3_init not every time we send
> an SGI.
>
We can move this check to gicv3_populate_rdist() which is called
for each cpu.
However we will miss check on mpidr value. But being MPIDR value which does
not change it should be ok to remove this check
>> +/*
>> + * Additional registers defined in GIC v3.
>> + * Common GICD registers are defined in gic.h
>> + */
>> +
>> +#define GICD_STATUSR (0x010)
>> [...][
>> +#define GICV3_GICD_PIDR0 (0x92)
>
> What is the distinction between variables with GIC[DR]_ prefixes and
> those with GICV3_GIC[DR]_ ones?
GICV3 is prefixed for indicating that there are values not the addresses.
In anycase I will remove GICV3 prefixes and postfix _VAL
Regards
Vijay
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 9:48 ` Vijay Kilari
@ 2014-07-22 10:01 ` Julien Grall
2014-07-22 10:43 ` Ian Campbell
2014-07-22 10:39 ` Ian Campbell
1 sibling, 1 reply; 38+ messages in thread
From: Julien Grall @ 2014-07-22 10:01 UTC (permalink / raw)
To: Vijay Kilari, Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Tim Deegan,
xen-devel@lists.xen.org, Stefano Stabellini, manish.jaggi
On 22/07/14 10:48, Vijay Kilari wrote:
>>> +/*
>>> + * Additional registers defined in GIC v3.
>>> + * Common GICD registers are defined in gic.h
>>> + */
>>> +
>>> +#define GICD_STATUSR (0x010)
>>> [...][
>>> +#define GICV3_GICD_PIDR0 (0x92)
>>
>> What is the distinction between variables with GIC[DR]_ prefixes and
>> those with GICV3_GIC[DR]_ ones?
>
> GICV3 is prefixed for indicating that there are values not the addresses.
> In anycase I will remove GICV3 prefixes and postfix _VAL
Those value are GICV3 specific. If you drop the prefix we won't know
what are their purpose...
--
Julien Grall
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 9:48 ` Vijay Kilari
2014-07-22 10:01 ` Julien Grall
@ 2014-07-22 10:39 ` Ian Campbell
2014-07-22 10:49 ` Vijay Kilari
1 sibling, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-22 10:39 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, 2014-07-22 at 15:18 +0530, Vijay Kilari wrote:
> On Wed, Jul 16, 2014 at 5:11 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> > On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
> >> +static inline void gicv3_restore_lrs(int nr_lrs, const struct vcpu *v)
> >> +static u16 gicv3_compute_target_list(int *base_cpu, const struct cpumask *mask,
> >> + uint64_t cluster_id)
> >> +{
> >> + int cpu = *base_cpu;
> >> + uint64_t mpidr = cpu_logical_map(cpu);
> >> + u16 tlist = 0;
> >> +
> >> + while ( cpu < nr_cpu_ids )
> >> + {
> >> + /*
> >> + * If we ever get a cluster of more than 16 CPUs, just
> >> + * scream and skip that CPU.
> >> + */
> >> + if ( (mpidr & 0xff) >= 16 )
> >
> > MPIPDR_EFF0_MASK if that's what this is, and at least once more in this
> > function.
> >
> >> + {
> >> + dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
> >> + goto out;
> >
> > Please validate this and complain in gicv3_init not every time we send
> > an SGI.
> >
>
> We can move this check to gicv3_populate_rdist() which is called
> for each cpu.
> However we will miss check on mpidr value. But being MPIDR value which does
> not change it should be ok to remove this check
Why isn't mpidr available at that point?
> >> + * Additional registers defined in GIC v3.
> >> + * Common GICD registers are defined in gic.h
> >> + */
> >> +
> >> +#define GICD_STATUSR (0x010)
> >> [...][
> >> +#define GICV3_GICD_PIDR0 (0x92)
> >
> > What is the distinction between variables with GIC[DR]_ prefixes and
> > those with GICV3_GIC[DR]_ ones?
>
> GICV3 is prefixed for indicating that there are values not the addresses.
> In anycase I will remove GICV3 prefixes and postfix _VAL
You mean the value used when emulating a read, I think?
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 10:01 ` Julien Grall
@ 2014-07-22 10:43 ` Ian Campbell
2014-07-22 11:13 ` Julien Grall
0 siblings, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-22 10:43 UTC (permalink / raw)
To: Julien Grall
Cc: Vijay Kilari, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, 2014-07-22 at 11:01 +0100, Julien Grall wrote:
>
> On 22/07/14 10:48, Vijay Kilari wrote:
> >>> +/*
> >>> + * Additional registers defined in GIC v3.
> >>> + * Common GICD registers are defined in gic.h
> >>> + */
> >>> +
> >>> +#define GICD_STATUSR (0x010)
> >>> [...][
> >>> +#define GICV3_GICD_PIDR0 (0x92)
> >>
> >> What is the distinction between variables with GIC[DR]_ prefixes and
> >> those with GICV3_GIC[DR]_ ones?
> >
> > GICV3 is prefixed for indicating that there are values not the addresses.
> > In anycase I will remove GICV3 prefixes and postfix _VAL
>
> Those value are GICV3 specific. If you drop the prefix we won't know
> what are their purpose...
I'm not so sure that's the case. We will know it is the value to use for
GICD_PIDR0 for any GIC which includes that register, which is at least
v3 and v4 right now. Calling it V3 is equally misleading as leaving it
out.
Given that we've decided to share the #defines across versions I think
we should leave the prefix off. The alternative is to make sure
everything is prefixed and to duplicate the definitions for each
version, which is an approach we previously moved away from I think, I
don't see a strong reason to go back on that decision now.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 10:39 ` Ian Campbell
@ 2014-07-22 10:49 ` Vijay Kilari
2014-07-22 10:55 ` Ian Campbell
0 siblings, 1 reply; 38+ messages in thread
From: Vijay Kilari @ 2014-07-22 10:49 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, Jul 22, 2014 at 4:09 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> On Tue, 2014-07-22 at 15:18 +0530, Vijay Kilari wrote:
>> On Wed, Jul 16, 2014 at 5:11 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
>> > On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
>> >> +static inline void gicv3_restore_lrs(int nr_lrs, const struct vcpu *v)
>> >> +static u16 gicv3_compute_target_list(int *base_cpu, const struct cpumask *mask,
>> >> + uint64_t cluster_id)
>> >> +{
>> >> + int cpu = *base_cpu;
>> >> + uint64_t mpidr = cpu_logical_map(cpu);
>> >> + u16 tlist = 0;
>> >> +
>> >> + while ( cpu < nr_cpu_ids )
>> >> + {
>> >> + /*
>> >> + * If we ever get a cluster of more than 16 CPUs, just
>> >> + * scream and skip that CPU.
>> >> + */
>> >> + if ( (mpidr & 0xff) >= 16 )
>> >
>> > MPIPDR_EFF0_MASK if that's what this is, and at least once more in this
>> > function.
>> >
>> >> + {
>> >> + dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
>> >> + goto out;
>> >
>> > Please validate this and complain in gicv3_init not every time we send
>> > an SGI.
>> >
>>
>> We can move this check to gicv3_populate_rdist() which is called
>> for each cpu.
>> However we will miss check on mpidr value. But being MPIDR value which does
>> not change it should be ok to remove this check
>
> Why isn't mpidr available at that point?
I mean check of mpidr value is not done here
(gicv3_compute_target_list()) to skip and
jump to out lable on wrong value of mpidr.
I have added following in gicv3_populate_rdist()
static int __init gicv3_populate_rdist(void)
{
int i;
uint32_t aff;
uint32_t reg;
uint64_t typer;
uint64_t mpidr = cpu_logical_map(smp_processor_id());
+ /*
+ * If we ever get a cluster of more than 16 CPUs, just scream.
+ */
+ if ( (mpidr & 0xff) >= 16 )
+ dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
>
>> >> + * Additional registers defined in GIC v3.
>> >> + * Common GICD registers are defined in gic.h
>> >> + */
>> >> +
>> >> +#define GICD_STATUSR (0x010)
>> >> [...][
>> >> +#define GICV3_GICD_PIDR0 (0x92)
>> >
>> > What is the distinction between variables with GIC[DR]_ prefixes and
>> > those with GICV3_GIC[DR]_ ones?
>>
>> GICV3 is prefixed for indicating that there are values not the addresses.
>> In anycase I will remove GICV3 prefixes and postfix _VAL
>
> You mean the value used when emulating a read, I think?
Yes, it is used in gicv3 driver for checking presence of re-distributor
and also in vgicv3 for emulating read.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 10:49 ` Vijay Kilari
@ 2014-07-22 10:55 ` Ian Campbell
2014-07-22 11:12 ` Vijay Kilari
0 siblings, 1 reply; 38+ messages in thread
From: Ian Campbell @ 2014-07-22 10:55 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, 2014-07-22 at 16:19 +0530, Vijay Kilari wrote:
> >
> >> >> + * Additional registers defined in GIC v3.
> >> >> + * Common GICD registers are defined in gic.h
> >> >> + */
> >> >> +
> >> >> +#define GICD_STATUSR (0x010)
> >> >> [...][
> >> >> +#define GICV3_GICD_PIDR0 (0x92)
> >> >
> >> > What is the distinction between variables with GIC[DR]_ prefixes and
> >> > those with GICV3_GIC[DR]_ ones?
> >>
> >> GICV3 is prefixed for indicating that there are values not the addresses.
> >> In anycase I will remove GICV3 prefixes and postfix _VAL
> >
> > You mean the value used when emulating a read, I think?
>
> Yes, it is used in gicv3 driver for checking presence of re-distributor
In the phsyical h/w? That sounds wrong. 0x92 is just one possible value
of this register (and the spec says it should be 0x94...). I don't see
you using this #define in that way anywhere though so perhaps I've
misunderstood.
> and also in vgicv3 for emulating read.
I wonder if we should instead propagate the underlying hardware value?
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 10:55 ` Ian Campbell
@ 2014-07-22 11:12 ` Vijay Kilari
2014-07-22 11:15 ` Julien Grall
0 siblings, 1 reply; 38+ messages in thread
From: Vijay Kilari @ 2014-07-22 11:12 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, Jul 22, 2014 at 4:25 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> On Tue, 2014-07-22 at 16:19 +0530, Vijay Kilari wrote:
>> >
>> >> >> + * Additional registers defined in GIC v3.
>> >> >> + * Common GICD registers are defined in gic.h
>> >> >> + */
>> >> >> +
>> >> >> +#define GICD_STATUSR (0x010)
>> >> >> [...][
>> >> >> +#define GICV3_GICD_PIDR0 (0x92)
>> >> >
>> >> > What is the distinction between variables with GIC[DR]_ prefixes and
>> >> > those with GICV3_GIC[DR]_ ones?
>> >>
>> >> GICV3 is prefixed for indicating that there are values not the addresses.
>> >> In anycase I will remove GICV3 prefixes and postfix _VAL
>> >
>> > You mean the value used when emulating a read, I think?
>>
>> Yes, it is used in gicv3 driver for checking presence of re-distributor
>
> In the phsyical h/w? That sounds wrong. 0x92 is just one possible value
> of this register (and the spec says it should be 0x94...). I don't see
> you using this #define in that way anywhere though so perhaps I've
> misunderstood.
I am using 20.0 version. which specifies 0x92 for ARM implementations of GICv3.
May be other vendors can use different value. So it is better propagate hw value
for emulation
GICD_PIDR0:
Bits [7:0]. Bits [7:0] of the ARM-defined DevID field. This field is 0x92 in
ARM implementations of a GICv3 or later Distributor.
In any case, GICD_PIDR0 is not used by gicv3 driver. GICD_PIDR2 & GICR_PIDR2 are
used where check is made on ARCH_REV [7:4]
>
>> and also in vgicv3 for emulating read.
>
> I wonder if we should instead propagate the underlying hardware value?
Yes,we can propagate hardware value.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 10:43 ` Ian Campbell
@ 2014-07-22 11:13 ` Julien Grall
2014-07-22 11:30 ` Vijay Kilari
0 siblings, 1 reply; 38+ messages in thread
From: Julien Grall @ 2014-07-22 11:13 UTC (permalink / raw)
To: Ian Campbell
Cc: Vijay Kilari, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On 22/07/14 11:43, Ian Campbell wrote:
> On Tue, 2014-07-22 at 11:01 +0100, Julien Grall wrote:
>>
>> On 22/07/14 10:48, Vijay Kilari wrote:
>>>>> +/*
>>>>> + * Additional registers defined in GIC v3.
>>>>> + * Common GICD registers are defined in gic.h
>>>>> + */
>>>>> +
>>>>> +#define GICD_STATUSR (0x010)
>>>>> [...][
>>>>> +#define GICV3_GICD_PIDR0 (0x92)
>>>>
>>>> What is the distinction between variables with GIC[DR]_ prefixes and
>>>> those with GICV3_GIC[DR]_ ones?
>>>
>>> GICV3 is prefixed for indicating that there are values not the addresses.
>>> In anycase I will remove GICV3 prefixes and postfix _VAL
>>
>> Those value are GICV3 specific. If you drop the prefix we won't know
>> what are their purpose...
>
> I'm not so sure that's the case. We will know it is the value to use for
> GICD_PIDR0 for any GIC which includes that register, which is at least
> v3 and v4 right now. Calling it V3 is equally misleading as leaving it
> out.
> Given that we've decided to share the #defines across versions I think
> we should leave the prefix off. The alternative is to make sure
> everything is prefixed and to duplicate the definitions for each
> version, which is an approach we previously moved away from I think, I
> don't see a strong reason to go back on that decision now.
On GICv2, this field is called ICPIDR0 (same register offset) and is
equal to 0x90.
If those values are only used for the vgic v3 driver, then they should
live in the c files and not in the common header.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 11:12 ` Vijay Kilari
@ 2014-07-22 11:15 ` Julien Grall
2014-07-22 11:19 ` Ian Campbell
0 siblings, 1 reply; 38+ messages in thread
From: Julien Grall @ 2014-07-22 11:15 UTC (permalink / raw)
To: Vijay Kilari, Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Tim Deegan,
xen-devel@lists.xen.org, Stefano Stabellini, manish.jaggi
On 22/07/14 12:12, Vijay Kilari wrote:
> On Tue, Jul 22, 2014 at 4:25 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
>> On Tue, 2014-07-22 at 16:19 +0530, Vijay Kilari wrote:
>>>>
>>>>>>> + * Additional registers defined in GIC v3.
>>>>>>> + * Common GICD registers are defined in gic.h
>>>>>>> + */
>>>>>>> +
>>>>>>> +#define GICD_STATUSR (0x010)
>>>>>>> [...][
>>>>>>> +#define GICV3_GICD_PIDR0 (0x92)
>>>>>>
>>>>>> What is the distinction between variables with GIC[DR]_ prefixes and
>>>>>> those with GICV3_GIC[DR]_ ones?
>>>>>
>>>>> GICV3 is prefixed for indicating that there are values not the addresses.
>>>>> In anycase I will remove GICV3 prefixes and postfix _VAL
>>>>
>>>> You mean the value used when emulating a read, I think?
>>>
>>> Yes, it is used in gicv3 driver for checking presence of re-distributor
>>
>> In the phsyical h/w? That sounds wrong. 0x92 is just one possible value
>> of this register (and the spec says it should be 0x94...). I don't see
>> you using this #define in that way anywhere though so perhaps I've
>> misunderstood.
>
> I am using 20.0 version. which specifies 0x92 for ARM implementations of GICv3.
> May be other vendors can use different value. So it is better propagate hw value
> for emulation
>
> GICD_PIDR0:
> Bits [7:0]. Bits [7:0] of the ARM-defined DevID field. This field is 0x92 in
> ARM implementations of a GICv3 or later Distributor.
>
> In any case, GICD_PIDR0 is not used by gicv3 driver. GICD_PIDR2 & GICR_PIDR2 are
> used where check is made on ARCH_REV [7:4]
>
>>
>>> and also in vgicv3 for emulating read.
>>
>> I wonder if we should instead propagate the underlying hardware value?
>
> Yes,we can propagate hardware value.
I don't think we should propagate the hardware value. We may emulate a
different distributor than the hardware one. In this case,
implementation defined register won't work as expected by the kernel.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 11:15 ` Julien Grall
@ 2014-07-22 11:19 ` Ian Campbell
0 siblings, 0 replies; 38+ messages in thread
From: Ian Campbell @ 2014-07-22 11:19 UTC (permalink / raw)
To: Julien Grall
Cc: Vijay Kilari, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, 2014-07-22 at 12:15 +0100, Julien Grall wrote:
>
> On 22/07/14 12:12, Vijay Kilari wrote:
> > On Tue, Jul 22, 2014 at 4:25 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> >> On Tue, 2014-07-22 at 16:19 +0530, Vijay Kilari wrote:
> >>>>
> >>>>>>> + * Additional registers defined in GIC v3.
> >>>>>>> + * Common GICD registers are defined in gic.h
> >>>>>>> + */
> >>>>>>> +
> >>>>>>> +#define GICD_STATUSR (0x010)
> >>>>>>> [...][
> >>>>>>> +#define GICV3_GICD_PIDR0 (0x92)
> >>>>>>
> >>>>>> What is the distinction between variables with GIC[DR]_ prefixes and
> >>>>>> those with GICV3_GIC[DR]_ ones?
> >>>>>
> >>>>> GICV3 is prefixed for indicating that there are values not the addresses.
> >>>>> In anycase I will remove GICV3 prefixes and postfix _VAL
> >>>>
> >>>> You mean the value used when emulating a read, I think?
> >>>
> >>> Yes, it is used in gicv3 driver for checking presence of re-distributor
> >>
> >> In the phsyical h/w? That sounds wrong. 0x92 is just one possible value
> >> of this register (and the spec says it should be 0x94...). I don't see
> >> you using this #define in that way anywhere though so perhaps I've
> >> misunderstood.
> >
> > I am using 20.0 version. which specifies 0x92 for ARM implementations of GICv3.
> > May be other vendors can use different value. So it is better propagate hw value
> > for emulation
> >
> > GICD_PIDR0:
> > Bits [7:0]. Bits [7:0] of the ARM-defined DevID field. This field is 0x92 in
> > ARM implementations of a GICv3 or later Distributor.
> >
> > In any case, GICD_PIDR0 is not used by gicv3 driver. GICD_PIDR2 & GICR_PIDR2 are
> > used where check is made on ARCH_REV [7:4]
> >
> >>
> >>> and also in vgicv3 for emulating read.
> >>
> >> I wonder if we should instead propagate the underlying hardware value?
> >
> > Yes,we can propagate hardware value.
>
> I don't think we should propagate the hardware value. We may emulate a
> different distributor than the hardware one. In this case,
> implementation defined register won't work as expected by the kernel.
Then we need to either get our own ID assigned (hard, I expect) or
commit to emulating whichever hardware we choose to expose. I don't
think emulating the ARM h/w would be a bad choice.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 11:13 ` Julien Grall
@ 2014-07-22 11:30 ` Vijay Kilari
2014-07-22 11:45 ` Ian Campbell
0 siblings, 1 reply; 38+ messages in thread
From: Vijay Kilari @ 2014-07-22 11:30 UTC (permalink / raw)
To: Julien Grall
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, Jul 22, 2014 at 4:43 PM, Julien Grall <julien.grall@linaro.org> wrote:
>
>
> On 22/07/14 11:43, Ian Campbell wrote:
>>
>> On Tue, 2014-07-22 at 11:01 +0100, Julien Grall wrote:
>>>
>>>
>>> On 22/07/14 10:48, Vijay Kilari wrote:
>>>>>>
>>>>>> +/*
>>>>>> + * Additional registers defined in GIC v3.
>>>>>> + * Common GICD registers are defined in gic.h
>>>>>> + */
>>>>>> +
>>>>>> +#define GICD_STATUSR (0x010)
>>>>>> [...][
>>>>>> +#define GICV3_GICD_PIDR0 (0x92)
>>>>>
>>>>>
>>>>> What is the distinction between variables with GIC[DR]_ prefixes and
>>>>> those with GICV3_GIC[DR]_ ones?
>>>>
>>>>
>>>> GICV3 is prefixed for indicating that there are values not the
>>>> addresses.
>>>> In anycase I will remove GICV3 prefixes and postfix _VAL
>>>
>>>
>>> Those value are GICV3 specific. If you drop the prefix we won't know
>>> what are their purpose...
>>
>>
>> I'm not so sure that's the case. We will know it is the value to use for
>> GICD_PIDR0 for any GIC which includes that register, which is at least
>> v3 and v4 right now. Calling it V3 is equally misleading as leaving it
>> out.
>> Given that we've decided to share the #defines across versions I think
>> we should leave the prefix off. The alternative is to make sure
>> everything is prefixed and to duplicate the definitions for each
>> version, which is an approach we previously moved away from I think, I
>> don't see a strong reason to go back on that decision now.
>
>
>
> On GICv2, this field is called ICPIDR0 (same register offset) and is equal
> to 0x90.
>
> If those values are only used for the vgic v3 driver, then they should live
> in the c files and not in the common header.
These PIDR values(not all) are used by both vgic-v3 and gicv3 driver. So those
are kept in common header file.
I plan to keep all defines without GICV3 prefix and add V3
specific one GICD_PIDR2_ARCH_V3_VAL
#define GICD_PIDR0_VAL (0x92)
#define GICD_PIDR1_VAL (0xb4)
-#define GICD_PIDR2_ARCH_VAL (0x30)
+#define GICD_PIDR2_ARCH_V3_VAL (0x3)
#define GICD_PIDR2_VAL (0x3b)
#define GICD_PIDR4_VAL (0x04)
#define GICD_PIDR2_ARCH_MASK (0xf0)
+#define GICD_PIDR2_ARCH_SHIFT (4)
#define GICR_PIDR0_VAL (0x93)
#define GICR_PIDR1_VAL GICD_PIDR1_VAL
-#define GICR_PIDR2_ARCH_VAL GICD_PIDR2_ARCH_VAL
+#define GICR_PIDR2_ARCH_V3_VAL GICD_PIDR2_ARCH_V3_VAL
#define GICR_PIDR2_VAL GICD_PIDR2_VAL
#define GICR_PIDR4_VAL GICD_PIDR4_VAL
#define GICR_PIDR2_ARCH_MASK GICD_PIDR2_ARCH_MASK
+#define GICR_PIDR2_ARCH_SHIFT GICD_PIDR2_ARCH_SHIFT
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 1/5] xen/arm: Add support for GIC v3
2014-07-22 11:30 ` Vijay Kilari
@ 2014-07-22 11:45 ` Ian Campbell
0 siblings, 0 replies; 38+ messages in thread
From: Ian Campbell @ 2014-07-22 11:45 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, 2014-07-22 at 17:00 +0530, Vijay Kilari wrote:
> On Tue, Jul 22, 2014 at 4:43 PM, Julien Grall <julien.grall@linaro.org> wrote:
> >
> >
> > On 22/07/14 11:43, Ian Campbell wrote:
> >>
> >> On Tue, 2014-07-22 at 11:01 +0100, Julien Grall wrote:
> >>>
> >>>
> >>> On 22/07/14 10:48, Vijay Kilari wrote:
> >>>>>>
> >>>>>> +/*
> >>>>>> + * Additional registers defined in GIC v3.
> >>>>>> + * Common GICD registers are defined in gic.h
> >>>>>> + */
> >>>>>> +
> >>>>>> +#define GICD_STATUSR (0x010)
> >>>>>> [...][
> >>>>>> +#define GICV3_GICD_PIDR0 (0x92)
> >>>>>
> >>>>>
> >>>>> What is the distinction between variables with GIC[DR]_ prefixes and
> >>>>> those with GICV3_GIC[DR]_ ones?
> >>>>
> >>>>
> >>>> GICV3 is prefixed for indicating that there are values not the
> >>>> addresses.
> >>>> In anycase I will remove GICV3 prefixes and postfix _VAL
> >>>
> >>>
> >>> Those value are GICV3 specific. If you drop the prefix we won't know
> >>> what are their purpose...
> >>
> >>
> >> I'm not so sure that's the case. We will know it is the value to use for
> >> GICD_PIDR0 for any GIC which includes that register, which is at least
> >> v3 and v4 right now. Calling it V3 is equally misleading as leaving it
> >> out.
> >> Given that we've decided to share the #defines across versions I think
> >> we should leave the prefix off. The alternative is to make sure
> >> everything is prefixed and to duplicate the definitions for each
> >> version, which is an approach we previously moved away from I think, I
> >> don't see a strong reason to go back on that decision now.
> >
> >
> >
> > On GICv2, this field is called ICPIDR0 (same register offset) and is equal
> > to 0x90.
> >
> > If those values are only used for the vgic v3 driver, then they should live
> > in the c files and not in the common header.
>
> These PIDR values(not all) are used by both vgic-v3 and gicv3 driver. So those
> are kept in common header file.
I think all that should be in the header file are the usual masks and
offsets used to decode the register and specific names defines to match
against. e.g. for PIDR2:
#define GICD_PIDR2_ARCH_REV_OFFSET (4)
#define GICD_PIDR2_ARCH_REV_MASK (0xf << GICD_PIDR2_ARCH_REV_OFFSET)
#define GICD_PIDR2_USES_JEP_MASK 0x08
#define GICD_PIDR2_JEP_ID_MASK 0x07
...
The gic code should use these to extract things it needs.
It would normally be OK to also define:
#define GICD_PIDR2_ARCH_GICV1 1
#define GICD_PIDR2_ARCH_GICV2 2
#define GICD_PIDR2_ARCH_GICV3 3
to compare against, but in this case since there is a 1:1 correspondence
there doesn't seem to be much point.
The vgic code might use these to construct a value, or might have a
local define or constant with a suitable comment.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-11 12:51 ` [PATCH v7 4/5] xen/arm: add SGI handling for GICv3 vijay.kilari
2014-07-11 13:43 ` Julien Grall
@ 2014-07-22 13:48 ` Stefano Stabellini
2014-07-22 14:13 ` Vijay Kilari
1 sibling, 1 reply; 38+ messages in thread
From: Stefano Stabellini @ 2014-07-22 13:48 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini, manish.jaggi
On Fri, 11 Jul 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
> Handle the trap and inject SGI to vcpu.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> ---
> v7: - Introduced callback for sysreg emulation
> - Removed unused parameter in inject_undef_exception()
> - Use inject_undef64_exception for reporting sysreg
> handling failure
>
> v6: - Removed forward declaration of vgic_to_sgi() in vgic-v3.c
> - Used vgic callback for SGI handling
> - Alignment changes
> ---
> xen/arch/arm/traps.c | 15 +++++++++++
> xen/arch/arm/vgic-v3.c | 52 +++++++++++++++++++++++++++++++++++++
> xen/arch/arm/vgic.c | 7 +++++
> xen/include/asm-arm/gic_v3_defs.h | 7 +++++
> xen/include/asm-arm/sysregs.h | 3 +++
> xen/include/asm-arm/vgic.h | 3 +++
> 6 files changed, 87 insertions(+)
>
> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> index 686d8b7..775bef1 100644
> --- a/xen/arch/arm/traps.c
> +++ b/xen/arch/arm/traps.c
> @@ -41,6 +41,7 @@
> #include "decode.h"
> #include "vtimer.h"
> #include <asm/gic.h>
> +#include <asm/vgic.h>
>
> /* The base of the stack must always be double-word aligned, which means
> * that both the kernel half of struct cpu_user_regs (which is pushed in
> @@ -1641,6 +1642,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
> domain_crash_synchronous();
> }
> break;
> + case HSR_SYSREG_ICC_SGI1R_EL1:
> + if ( !vgic_emulate(regs, hsr) )
> + {
> + dprintk(XENLOG_WARNING,
> + "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
> + inject_undef64_exception(regs, hsr.len);
> + }
> + break;
> + case HSR_SYSREG_ICC_SGI0R_EL1:
> + case HSR_SYSREG_ICC_ASGI1R_EL1:
> + /* TBD: Implement to support secure grp0/1 SGI forwarding */
> + dprintk(XENLOG_WARNING,
> + "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n");
> + inject_undef64_exception(regs, hsr.len);
> default:
> bad_sysreg:
> {
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 2bf0e7c..feee486 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -834,6 +834,57 @@ write_ignore_64:
> return 1;
> }
>
> +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
> +{
> + int virq;
> + int irqmode;
> + enum gic_sgi_mode sgi_mode;
> + unsigned long vcpu_mask = 0;
> +
> + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
> + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
> + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
> +
> + /* Map GIC sgi value to enum value */
> + switch ( irqmode )
> + {
> + case ICH_SGI_TARGET_LIST:
> + sgi_mode = SGI_TARGET_LIST;
> + break;
> + case ICH_SGI_TARGET_OTHERS:
> + sgi_mode = SGI_TARGET_OTHERS;
> + break;
> + default:
> + BUG();
You haven't addressed my previous comments (or replied to them if you
disagree):
http://marc.info/?l=xen-devel&m=140259344723979
http://marc.info/?l=xen-devel&m=140259388524231
> + }
> +
> + return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
> +}
> +
> +static int vgicv3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr)
> +{
> + struct vcpu *v = current;
> + struct hsr_sysreg sysreg = hsr.sysreg;
> + register_t *r = select_user_reg(regs, sysreg.reg);
> +
> + ASSERT (hsr.ec == HSR_EC_SYSREG);
> +
> + switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
> + {
> + case HSR_SYSREG_ICC_SGI1R_EL1:
> + /* WO */
> + if ( !sysreg.read )
> + return vgicv3_to_sgi(v, *r);
> + else
> + {
> + gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
> + return 0;
> + }
> + default:
> + return 0;
> + }
> +}
> +
> static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
> .read_handler = vgic_v3_rdistr_mmio_read,
> .write_handler = vgic_v3_rdistr_mmio_write,
> @@ -884,6 +935,7 @@ static int vgicv3_domain_init(struct domain *d)
> static const struct vgic_ops v3_ops = {
> .vcpu_init = vgicv3_vcpu_init,
> .domain_init = vgicv3_domain_init,
> + .emulate_sysreg = vgicv3_emulate_sysreg,
> };
>
> int vgic_v3_init(struct domain *d)
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 3647497..e15d509 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -343,6 +343,13 @@ out:
> smp_send_event_check_mask(cpumask_of(v->processor));
> }
>
> +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
> +{
> + struct vcpu *v = current;
> +
> + return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
> index 1c32e0c..b94ba20 100644
> --- a/xen/include/asm-arm/gic_v3_defs.h
> +++ b/xen/include/asm-arm/gic_v3_defs.h
> @@ -147,6 +147,13 @@
> #define GICH_VMCR_PRIORITY_MASK 0xff
> #define GICH_VMCR_PRIORITY_SHIFT 24
>
> +#define ICH_SGI_IRQMODE_SHIFT 40
> +#define ICH_SGI_IRQMODE_MASK 0x1
> +#define ICH_SGI_TARGET_OTHERS 1
> +#define ICH_SGI_TARGET_LIST 0
> +#define ICH_SGI_IRQ_SHIFT 24
> +#define ICH_SGI_IRQ_MASK 0xf
> +#define ICH_SGI_TARGETLIST_MASK 0xffff
> #endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
>
> /*
> diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
> index b00871c..48ea498 100644
> --- a/xen/include/asm-arm/sysregs.h
> +++ b/xen/include/asm-arm/sysregs.h
> @@ -78,6 +78,9 @@
> #define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2)
> #define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0)
> #define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0)
> +#define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5)
> +#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
> +#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7)
> #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
>
> #define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0)
> diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
> index f580b78..63ecfa1 100644
> --- a/xen/include/asm-arm/vgic.h
> +++ b/xen/include/asm-arm/vgic.h
> @@ -98,6 +98,8 @@ struct vgic_ops {
> int (*vcpu_init)(struct vcpu *v);
> /* Domain specific initialization of vGIC */
> int (*domain_init)(struct domain *d);
> + /* vGIC sysreg emulation */
> + int (*emulate_sysreg)(struct cpu_user_regs *regs, union hsr hsr);
> };
>
> /* Number of ranks of interrupt registers for a domain */
> @@ -165,6 +167,7 @@ extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
> extern void vgic_clear_pending_irqs(struct vcpu *v);
> extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
> extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s);
> +extern int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr);
> extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
> extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
> extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-22 13:48 ` Stefano Stabellini
@ 2014-07-22 14:13 ` Vijay Kilari
2014-07-23 5:48 ` Vijay Kilari
0 siblings, 1 reply; 38+ messages in thread
From: Vijay Kilari @ 2014-07-22 14:13 UTC (permalink / raw)
To: Stefano Stabellini
Cc: Ian Campbell, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, Jul 22, 2014 at 7:18 PM, Stefano Stabellini
<stefano.stabellini@eu.citrix.com> wrote:
> On Fri, 11 Jul 2014, vijay.kilari@gmail.com wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>
>> In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
>> Handle the trap and inject SGI to vcpu.
>>
>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>> ---
>> v7: - Introduced callback for sysreg emulation
>> - Removed unused parameter in inject_undef_exception()
>> - Use inject_undef64_exception for reporting sysreg
>> handling failure
>>
>> v6: - Removed forward declaration of vgic_to_sgi() in vgic-v3.c
>> - Used vgic callback for SGI handling
>> - Alignment changes
>> ---
>> xen/arch/arm/traps.c | 15 +++++++++++
>> xen/arch/arm/vgic-v3.c | 52 +++++++++++++++++++++++++++++++++++++
>> xen/arch/arm/vgic.c | 7 +++++
>> xen/include/asm-arm/gic_v3_defs.h | 7 +++++
>> xen/include/asm-arm/sysregs.h | 3 +++
>> xen/include/asm-arm/vgic.h | 3 +++
>> 6 files changed, 87 insertions(+)
>>
>> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
>> index 686d8b7..775bef1 100644
>> --- a/xen/arch/arm/traps.c
>> +++ b/xen/arch/arm/traps.c
>> @@ -41,6 +41,7 @@
>> #include "decode.h"
>> #include "vtimer.h"
>> #include <asm/gic.h>
>> +#include <asm/vgic.h>
>>
>> /* The base of the stack must always be double-word aligned, which means
>> * that both the kernel half of struct cpu_user_regs (which is pushed in
>> @@ -1641,6 +1642,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
>> domain_crash_synchronous();
>> }
>> break;
>> + case HSR_SYSREG_ICC_SGI1R_EL1:
>> + if ( !vgic_emulate(regs, hsr) )
>> + {
>> + dprintk(XENLOG_WARNING,
>> + "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
>> + inject_undef64_exception(regs, hsr.len);
>> + }
>> + break;
>> + case HSR_SYSREG_ICC_SGI0R_EL1:
>> + case HSR_SYSREG_ICC_ASGI1R_EL1:
>> + /* TBD: Implement to support secure grp0/1 SGI forwarding */
>> + dprintk(XENLOG_WARNING,
>> + "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n");
>> + inject_undef64_exception(regs, hsr.len);
>> default:
>> bad_sysreg:
>> {
>> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
>> index 2bf0e7c..feee486 100644
>> --- a/xen/arch/arm/vgic-v3.c
>> +++ b/xen/arch/arm/vgic-v3.c
>> @@ -834,6 +834,57 @@ write_ignore_64:
>> return 1;
>> }
>>
>> +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
>> +{
>> + int virq;
>> + int irqmode;
>> + enum gic_sgi_mode sgi_mode;
>> + unsigned long vcpu_mask = 0;
>> +
>> + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
>> + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
>> + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
>> +
>> + /* Map GIC sgi value to enum value */
>> + switch ( irqmode )
>> + {
>> + case ICH_SGI_TARGET_LIST:
>> + sgi_mode = SGI_TARGET_LIST;
>> + break;
>> + case ICH_SGI_TARGET_OTHERS:
>> + sgi_mode = SGI_TARGET_OTHERS;
>> + break;
>> + default:
>> + BUG();
>
> You haven't addressed my previous comments (or replied to them if you
> disagree):
>
> http://marc.info/?l=xen-devel&m=140259344723979
OK. A warning and return 0 will address the issue
> http://marc.info/?l=xen-devel&m=140259388524231
OK. I will take care in next version
>
>
>> + }
>> +
>> + return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
>> +}
>> +
>> +static int vgicv3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr)
>> +{
>> + struct vcpu *v = current;
>> + struct hsr_sysreg sysreg = hsr.sysreg;
>> + register_t *r = select_user_reg(regs, sysreg.reg);
>> +
>> + ASSERT (hsr.ec == HSR_EC_SYSREG);
>> +
>> + switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
>> + {
>> + case HSR_SYSREG_ICC_SGI1R_EL1:
>> + /* WO */
>> + if ( !sysreg.read )
>> + return vgicv3_to_sgi(v, *r);
>> + else
>> + {
>> + gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
>> + return 0;
>> + }
>> + default:
>> + return 0;
>> + }
>> +}
>> +
>> static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
>> .read_handler = vgic_v3_rdistr_mmio_read,
>> .write_handler = vgic_v3_rdistr_mmio_write,
>> @@ -884,6 +935,7 @@ static int vgicv3_domain_init(struct domain *d)
>> static const struct vgic_ops v3_ops = {
>> .vcpu_init = vgicv3_vcpu_init,
>> .domain_init = vgicv3_domain_init,
>> + .emulate_sysreg = vgicv3_emulate_sysreg,
>> };
>>
>> int vgic_v3_init(struct domain *d)
>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>> index 3647497..e15d509 100644
>> --- a/xen/arch/arm/vgic.c
>> +++ b/xen/arch/arm/vgic.c
>> @@ -343,6 +343,13 @@ out:
>> smp_send_event_check_mask(cpumask_of(v->processor));
>> }
>>
>> +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
>> +{
>> + struct vcpu *v = current;
>> +
>> + return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
>> +}
>> +
>> /*
>> * Local variables:
>> * mode: C
>> diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
>> index 1c32e0c..b94ba20 100644
>> --- a/xen/include/asm-arm/gic_v3_defs.h
>> +++ b/xen/include/asm-arm/gic_v3_defs.h
>> @@ -147,6 +147,13 @@
>> #define GICH_VMCR_PRIORITY_MASK 0xff
>> #define GICH_VMCR_PRIORITY_SHIFT 24
>>
>> +#define ICH_SGI_IRQMODE_SHIFT 40
>> +#define ICH_SGI_IRQMODE_MASK 0x1
>> +#define ICH_SGI_TARGET_OTHERS 1
>> +#define ICH_SGI_TARGET_LIST 0
>> +#define ICH_SGI_IRQ_SHIFT 24
>> +#define ICH_SGI_IRQ_MASK 0xf
>> +#define ICH_SGI_TARGETLIST_MASK 0xffff
>> #endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
>>
>> /*
>> diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
>> index b00871c..48ea498 100644
>> --- a/xen/include/asm-arm/sysregs.h
>> +++ b/xen/include/asm-arm/sysregs.h
>> @@ -78,6 +78,9 @@
>> #define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2)
>> #define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0)
>> #define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0)
>> +#define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5)
>> +#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
>> +#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7)
>> #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
>>
>> #define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0)
>> diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
>> index f580b78..63ecfa1 100644
>> --- a/xen/include/asm-arm/vgic.h
>> +++ b/xen/include/asm-arm/vgic.h
>> @@ -98,6 +98,8 @@ struct vgic_ops {
>> int (*vcpu_init)(struct vcpu *v);
>> /* Domain specific initialization of vGIC */
>> int (*domain_init)(struct domain *d);
>> + /* vGIC sysreg emulation */
>> + int (*emulate_sysreg)(struct cpu_user_regs *regs, union hsr hsr);
>> };
>>
>> /* Number of ranks of interrupt registers for a domain */
>> @@ -165,6 +167,7 @@ extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
>> extern void vgic_clear_pending_irqs(struct vcpu *v);
>> extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
>> extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s);
>> +extern int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr);
>> extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
>> extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
>> extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
>> --
>> 1.7.9.5
>>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-22 14:13 ` Vijay Kilari
@ 2014-07-23 5:48 ` Vijay Kilari
2014-07-23 10:35 ` Stefano Stabellini
0 siblings, 1 reply; 38+ messages in thread
From: Vijay Kilari @ 2014-07-23 5:48 UTC (permalink / raw)
To: Stefano Stabellini
Cc: Ian Campbell, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Tue, Jul 22, 2014 at 7:43 PM, Vijay Kilari <vijay.kilari@gmail.com> wrote:
> On Tue, Jul 22, 2014 at 7:18 PM, Stefano Stabellini
> <stefano.stabellini@eu.citrix.com> wrote:
>> On Fri, 11 Jul 2014, vijay.kilari@gmail.com wrote:
>>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>>
>>> In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
>>> Handle the trap and inject SGI to vcpu.
>>>
>>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>> ---
>>> v7: - Introduced callback for sysreg emulation
>>> - Removed unused parameter in inject_undef_exception()
>>> - Use inject_undef64_exception for reporting sysreg
>>> handling failure
>>>
>>> v6: - Removed forward declaration of vgic_to_sgi() in vgic-v3.c
>>> - Used vgic callback for SGI handling
>>> - Alignment changes
>>> ---
>>> xen/arch/arm/traps.c | 15 +++++++++++
>>> xen/arch/arm/vgic-v3.c | 52 +++++++++++++++++++++++++++++++++++++
>>> xen/arch/arm/vgic.c | 7 +++++
>>> xen/include/asm-arm/gic_v3_defs.h | 7 +++++
>>> xen/include/asm-arm/sysregs.h | 3 +++
>>> xen/include/asm-arm/vgic.h | 3 +++
>>> 6 files changed, 87 insertions(+)
>>>
>>> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
>>> index 686d8b7..775bef1 100644
>>> --- a/xen/arch/arm/traps.c
>>> +++ b/xen/arch/arm/traps.c
>>> @@ -41,6 +41,7 @@
>>> #include "decode.h"
>>> #include "vtimer.h"
>>> #include <asm/gic.h>
>>> +#include <asm/vgic.h>
>>>
>>> /* The base of the stack must always be double-word aligned, which means
>>> * that both the kernel half of struct cpu_user_regs (which is pushed in
>>> @@ -1641,6 +1642,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
>>> domain_crash_synchronous();
>>> }
>>> break;
>>> + case HSR_SYSREG_ICC_SGI1R_EL1:
>>> + if ( !vgic_emulate(regs, hsr) )
>>> + {
>>> + dprintk(XENLOG_WARNING,
>>> + "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
>>> + inject_undef64_exception(regs, hsr.len);
>>> + }
>>> + break;
>>> + case HSR_SYSREG_ICC_SGI0R_EL1:
>>> + case HSR_SYSREG_ICC_ASGI1R_EL1:
>>> + /* TBD: Implement to support secure grp0/1 SGI forwarding */
>>> + dprintk(XENLOG_WARNING,
>>> + "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n");
>>> + inject_undef64_exception(regs, hsr.len);
>>> default:
>>> bad_sysreg:
>>> {
>>> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
>>> index 2bf0e7c..feee486 100644
>>> --- a/xen/arch/arm/vgic-v3.c
>>> +++ b/xen/arch/arm/vgic-v3.c
>>> @@ -834,6 +834,57 @@ write_ignore_64:
>>> return 1;
>>> }
>>>
>>> +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
>>> +{
>>> + int virq;
>>> + int irqmode;
>>> + enum gic_sgi_mode sgi_mode;
>>> + unsigned long vcpu_mask = 0;
>>> +
>>> + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
>>> + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
>>> + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
>>> +
>>> + /* Map GIC sgi value to enum value */
>>> + switch ( irqmode )
>>> + {
>>> + case ICH_SGI_TARGET_LIST:
>>> + sgi_mode = SGI_TARGET_LIST;
>>> + break;
>>> + case ICH_SGI_TARGET_OTHERS:
>>> + sgi_mode = SGI_TARGET_OTHERS;
>>> + break;
>>> + default:
>>> + BUG();
>>
>> You haven't addressed my previous comments (or replied to them if you
>> disagree):
>>
>> http://marc.info/?l=xen-devel&m=140259344723979
>
> OK. A warning and return 0 will address the issue
>
>> http://marc.info/?l=xen-devel&m=140259388524231
SGI's are injected at Rdist-0 level. So affinity 1,2,3 levels are ignored
Do we still need a comment?
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
2014-07-23 5:48 ` Vijay Kilari
@ 2014-07-23 10:35 ` Stefano Stabellini
0 siblings, 0 replies; 38+ messages in thread
From: Stefano Stabellini @ 2014-07-23 10:35 UTC (permalink / raw)
To: Vijay Kilari
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Julien Grall, Tim Deegan, xen-devel@lists.xen.org,
Stefano Stabellini, manish.jaggi
On Wed, 23 Jul 2014, Vijay Kilari wrote:
> On Tue, Jul 22, 2014 at 7:43 PM, Vijay Kilari <vijay.kilari@gmail.com> wrote:
> > On Tue, Jul 22, 2014 at 7:18 PM, Stefano Stabellini
> > <stefano.stabellini@eu.citrix.com> wrote:
> >> On Fri, 11 Jul 2014, vijay.kilari@gmail.com wrote:
> >>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >>>
> >>> In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
> >>> Handle the trap and inject SGI to vcpu.
> >>>
> >>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >>> ---
> >>> v7: - Introduced callback for sysreg emulation
> >>> - Removed unused parameter in inject_undef_exception()
> >>> - Use inject_undef64_exception for reporting sysreg
> >>> handling failure
> >>>
> >>> v6: - Removed forward declaration of vgic_to_sgi() in vgic-v3.c
> >>> - Used vgic callback for SGI handling
> >>> - Alignment changes
> >>> ---
> >>> xen/arch/arm/traps.c | 15 +++++++++++
> >>> xen/arch/arm/vgic-v3.c | 52 +++++++++++++++++++++++++++++++++++++
> >>> xen/arch/arm/vgic.c | 7 +++++
> >>> xen/include/asm-arm/gic_v3_defs.h | 7 +++++
> >>> xen/include/asm-arm/sysregs.h | 3 +++
> >>> xen/include/asm-arm/vgic.h | 3 +++
> >>> 6 files changed, 87 insertions(+)
> >>>
> >>> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> >>> index 686d8b7..775bef1 100644
> >>> --- a/xen/arch/arm/traps.c
> >>> +++ b/xen/arch/arm/traps.c
> >>> @@ -41,6 +41,7 @@
> >>> #include "decode.h"
> >>> #include "vtimer.h"
> >>> #include <asm/gic.h>
> >>> +#include <asm/vgic.h>
> >>>
> >>> /* The base of the stack must always be double-word aligned, which means
> >>> * that both the kernel half of struct cpu_user_regs (which is pushed in
> >>> @@ -1641,6 +1642,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
> >>> domain_crash_synchronous();
> >>> }
> >>> break;
> >>> + case HSR_SYSREG_ICC_SGI1R_EL1:
> >>> + if ( !vgic_emulate(regs, hsr) )
> >>> + {
> >>> + dprintk(XENLOG_WARNING,
> >>> + "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
> >>> + inject_undef64_exception(regs, hsr.len);
> >>> + }
> >>> + break;
> >>> + case HSR_SYSREG_ICC_SGI0R_EL1:
> >>> + case HSR_SYSREG_ICC_ASGI1R_EL1:
> >>> + /* TBD: Implement to support secure grp0/1 SGI forwarding */
> >>> + dprintk(XENLOG_WARNING,
> >>> + "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n");
> >>> + inject_undef64_exception(regs, hsr.len);
> >>> default:
> >>> bad_sysreg:
> >>> {
> >>> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> >>> index 2bf0e7c..feee486 100644
> >>> --- a/xen/arch/arm/vgic-v3.c
> >>> +++ b/xen/arch/arm/vgic-v3.c
> >>> @@ -834,6 +834,57 @@ write_ignore_64:
> >>> return 1;
> >>> }
> >>>
> >>> +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
> >>> +{
> >>> + int virq;
> >>> + int irqmode;
> >>> + enum gic_sgi_mode sgi_mode;
> >>> + unsigned long vcpu_mask = 0;
> >>> +
> >>> + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
> >>> + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
> >>> + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
> >>> +
> >>> + /* Map GIC sgi value to enum value */
> >>> + switch ( irqmode )
> >>> + {
> >>> + case ICH_SGI_TARGET_LIST:
> >>> + sgi_mode = SGI_TARGET_LIST;
> >>> + break;
> >>> + case ICH_SGI_TARGET_OTHERS:
> >>> + sgi_mode = SGI_TARGET_OTHERS;
> >>> + break;
> >>> + default:
> >>> + BUG();
> >>
> >> You haven't addressed my previous comments (or replied to them if you
> >> disagree):
> >>
> >> http://marc.info/?l=xen-devel&m=140259344723979
> >
> > OK. A warning and return 0 will address the issue
> >
> >> http://marc.info/?l=xen-devel&m=140259388524231
>
> SGI's are injected at Rdist-0 level. So affinity 1,2,3 levels are ignored
> Do we still need a comment?
I couldn't hurt
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 0/5] xen/arm: Add GICv3 support
2014-07-16 13:32 ` Ian Campbell
@ 2014-07-23 10:51 ` Vijay Kilari
2014-07-23 11:31 ` Ian Campbell
0 siblings, 1 reply; 38+ messages in thread
From: Vijay Kilari @ 2014-07-23 10:51 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Wed, Jul 16, 2014 at 7:02 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> On Wed, 2014-07-16 at 13:38 +0100, Ian Campbell wrote:
>> On Wed, 2014-07-16 at 17:17 +0530, Vijay Kilari wrote:
>> > On Wed, Jul 16, 2014 at 4:05 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
>> > > On Fri, 2014-07-11 at 18:21 +0530, vijay.kilari@gmail.com wrote:
>> > >> Add GICv3 support for arm64 platform.
>> > >
>> > > I get lots of:
>> > > {standard input}:1476: Error: unknown or missing system register name at operand 1 -- `msr ICH_VMCR_EL2,x1'
>> > >
>> > > I'm using:
>> > > $ aarch64-linux-gnu-gcc --version
>> > > aarch64-linux-gnu-gcc (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04) 4.8.3 20140401 (prerelease)
>> > >
>> > > Do you have a pointer to a toolchain which can build this stuff?
>> >
>> > I am using our internal toolchain based on GCC version 4.7
>>
>> OK. We really ought to find some publicly available toolchain before
>> accepting this code. Or else we need to make gic v3 functionality depend
>> on the toolstack, which would suck.
>>
>> I'm going to see if the Linaro 4.9 gcc will do it.
>
> Sadly not.
>
> Mark Rutland pointed me to the workaround which Linux uses:
> https://git.kernel.org/cgit/linux/kernel/git/maz/arm-platforms.git/tree/include/linux/irqchip/arm-gic-v3.h?h=gicv3/base&id=1545387f2ca2e51f5ccd3ed764348ee41e15c02f#n143
>
> Which AFAICT works with at least Linaro's gcc 4.8 and 4.9. So I think
> we'll have to go down this route.
>
> Please could you make sure that this series compiles with the gcc from
> either http://releases.linaro.org/14.04/components/toolchain/binaries
> or
> http://releases.linaro.org/14.06/components/toolchain/binaries
>
> Presumably this will mostly be a case of adding the defines to
> xen/include/asm-arm/sysregs.h.
After adding assembler aliases to GIC sysregs similar to Mark's workaround,
I observed that existing READ_SYSREG{32,64} and WRITE_SYSREG{32,64}
macros does not replace the assembler aliases. Instead register names are kept
as it is.
However {READ,WRITE}_SYSREG macros works because these macros
are again replaced with {READ,WRITE}_SYSREG64 macro. So pre-processor
will replace the sys register name with assembler alias when replacing
{READ,WRITE}_SYSREG macro with {READ,WRITE}_SYSREG64 macro
I propose to change existing READ_SYSREG{32,64} and WRITE_SYSREG{32,64}
macros
+#define __stringyfy(x) #x
/* Access to system registers */
#define READ_SYSREG32(name) ({ \
uint32_t _r; \
- asm volatile("mrs %0, "#name : "=r" (_r)); \
+ asm volatile("mrs %0, "__stringyfy(name) : "=r" (_r)); \
_r; })
#define WRITE_SYSREG32(v, name) do { \
uint32_t _r = v; \
- asm volatile("msr "#name", %0" : : "r" (_r)); \
+ asm volatile("msr "__stringyfy(name)", %0" : : "r" (_r)); \
} while (0)
#define WRITE_SYSREG64(v, name) do { \
uint64_t _r = v; \
- asm volatile("msr "#name", %0" : : "r" (_r)); \
+ asm volatile("msr "__stringyfy(name)", %0" : : "r" (_r)); \
} while (0)
#define READ_SYSREG64(name) ({ \
uint64_t _r; \
- asm volatile("mrs %0, "#name : "=r" (_r)); \
+ asm volatile("mrs %0, "__stringyfy(name) : "=r" (_r)); \
_r; })
May be __stringyfy macro can be added to separate header
file similar to kernel?
Regards
Vijay
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v7 0/5] xen/arm: Add GICv3 support
2014-07-23 10:51 ` Vijay Kilari
@ 2014-07-23 11:31 ` Ian Campbell
0 siblings, 0 replies; 38+ messages in thread
From: Ian Campbell @ 2014-07-23 11:31 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel@lists.xen.org, Stefano Stabellini,
manish.jaggi
On Wed, 2014-07-23 at 16:21 +0530, Vijay Kilari wrote:
> I propose to change existing READ_SYSREG{32,64} and WRITE_SYSREG{32,64}
> macros
>
> +#define __stringyfy(x) #x
Please use <xen/stringify.h>
> /* Access to system registers */
>
> #define READ_SYSREG32(name) ({ \
> uint32_t _r; \
> - asm volatile("mrs %0, "#name : "=r" (_r)); \
> + asm volatile("mrs %0, "__stringyfy(name) : "=r" (_r)); \
> _r; })
> #define WRITE_SYSREG32(v, name) do { \
> uint32_t _r = v; \
> - asm volatile("msr "#name", %0" : : "r" (_r)); \
> + asm volatile("msr "__stringyfy(name)", %0" : : "r" (_r)); \
> } while (0)
>
> #define WRITE_SYSREG64(v, name) do { \
> uint64_t _r = v; \
> - asm volatile("msr "#name", %0" : : "r" (_r)); \
> + asm volatile("msr "__stringyfy(name)", %0" : : "r" (_r)); \
> } while (0)
> #define READ_SYSREG64(name) ({ \
> uint64_t _r; \
> - asm volatile("mrs %0, "#name : "=r" (_r)); \
> + asm volatile("mrs %0, "__stringyfy(name) : "=r" (_r)); \
> _r; })
>
> May be __stringyfy macro can be added to separate header
> file similar to kernel?
Heh, I should read to the end ;-)
The change looks fine in principal, please do it in a patch of its own.
Ian.
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2014-07-23 11:31 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-07-11 12:51 [PATCH v7 0/5] xen/arm: Add GICv3 support vijay.kilari
2014-07-11 12:51 ` [PATCH v7 1/5] xen/arm: Add support for GIC v3 vijay.kilari
2014-07-16 11:41 ` Ian Campbell
2014-07-22 9:48 ` Vijay Kilari
2014-07-22 10:01 ` Julien Grall
2014-07-22 10:43 ` Ian Campbell
2014-07-22 11:13 ` Julien Grall
2014-07-22 11:30 ` Vijay Kilari
2014-07-22 11:45 ` Ian Campbell
2014-07-22 10:39 ` Ian Campbell
2014-07-22 10:49 ` Vijay Kilari
2014-07-22 10:55 ` Ian Campbell
2014-07-22 11:12 ` Vijay Kilari
2014-07-22 11:15 ` Julien Grall
2014-07-22 11:19 ` Ian Campbell
2014-07-11 12:51 ` [PATCH v7 2/5] xen/arm: Add virtual GICv3 support vijay.kilari
2014-07-14 15:59 ` Julien Grall
2014-07-16 11:47 ` Ian Campbell
2014-07-16 11:56 ` Vijay Kilari
2014-07-11 12:51 ` [PATCH v7 3/5] xen/arm: Update Dom0 GIC dt node with GICv3 information vijay.kilari
2014-07-16 11:53 ` Ian Campbell
2014-07-11 12:51 ` [PATCH v7 4/5] xen/arm: add SGI handling for GICv3 vijay.kilari
2014-07-11 13:43 ` Julien Grall
2014-07-11 14:08 ` Ian Campbell
2014-07-11 14:12 ` Julien Grall
2014-07-11 14:18 ` Ian Campbell
2014-07-22 13:48 ` Stefano Stabellini
2014-07-22 14:13 ` Vijay Kilari
2014-07-23 5:48 ` Vijay Kilari
2014-07-23 10:35 ` Stefano Stabellini
2014-07-11 12:51 ` [PATCH v7 5/5] xen/arm: check for GICv3 platform support vijay.kilari
2014-07-16 12:11 ` Ian Campbell
2014-07-16 10:35 ` [PATCH v7 0/5] xen/arm: Add GICv3 support Ian Campbell
2014-07-16 11:47 ` Vijay Kilari
2014-07-16 12:38 ` Ian Campbell
2014-07-16 13:32 ` Ian Campbell
2014-07-23 10:51 ` Vijay Kilari
2014-07-23 11:31 ` Ian Campbell
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