From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= Subject: Re: [PATCH v4 3/4] amd-iommu: disable iommu_hap_pt_share with AMD IOMMUs Date: Tue, 22 Jul 2014 19:39:57 +0200 Message-ID: <53CEA1ED.1050604@citrix.com> References: <1401876381-42977-1-git-send-email-roger.pau@citrix.com> <1401876381-42977-4-git-send-email-roger.pau@citrix.com> <53CE9FAC.8070008@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X9e2m-0006eA-HL for xen-devel@lists.xenproject.org; Tue, 22 Jul 2014 17:40:04 +0000 In-Reply-To: <53CE9FAC.8070008@amd.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Suravee Suthikulpanit , "xen-devel@lists.xenproject.org" Cc: Jan Beulich , Xiantao Zhang List-Id: xen-devel@lists.xenproject.org On 22/07/14 19:30, Suravee Suthikulpanit wrote: > Roger, > > I am not quite sure why you would disable "iommu_hap_pt_share" for AMD > IOMMU. The current implementation assumes that the p2m can be shared. > > Also, I feel that simply just set iommu_hap_pt_share = 0 (while still > having several places in the AMD iommu drivers and p2m-pt.c assuming > that it can be shared) seems a bit messy. According to the comment in p2m.h, AMD IOMMU only supports bit 52 to bit 58 in the pte to be 0, otherwise the hw generates page faults. If we want to support doing IO to devices behind an IOMMU from page types different than p2m_ram_rw the p2m tables cannot be shared, because the bits from 52 to 58 will indeed be different than 0, and will generate page faults. Roger.