From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH] xen: arm: Write to the correct PT when mapping the DTB on boot on arm64 Date: Fri, 25 Jul 2014 13:12:54 +0100 Message-ID: <53D249C6.70204@linaro.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel@lists.xen.org Cc: tim@xen.org, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org On 07/25/2014 10:32 AM, Ian Campbell wrote: > We currently get away with this because when debug=y and earlyprintk is enabled > the previous block of (conditinal) code would have set this up. Historically we NIT: conditional > mostly got away with it even without those options because the pre paging code > would normally (at least on h/w we test) leave x4 set to the paddr of > boot_second. > > This latent bug has always been present but was exposed by ca59618967fe "xen: > arm: Handle 4K aligned hypervisor load address" (or one of the related patches) > since now x4 is quite likely to point to boot_third not boot_second. > > Signed-off-by: Ian Campbell Acked-by: Julien Grall Regards, > --- > xen/arch/arm/arm64/head.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S > index dcb7071..43b5e72 100644 > --- a/xen/arch/arm/arm64/head.S > +++ b/xen/arch/arm/arm64/head.S > @@ -428,6 +428,7 @@ paging: > /* Map the DTB in the boot misc slot */ > cbnz x22, 1f /* Only on boot CPU */ > > + ldr x4, =boot_second /* x4 := vaddr (boot_second) */ > lsr x2, x21, #SECOND_SHIFT > lsl x2, x2, #SECOND_SHIFT /* x2 := 2MB-aligned paddr of DTB */ > mov x3, #PT_MEM /* x2 := 2MB RAM incl. DTB */ > -- Julien Grall