From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH v8 4/7] xen/arm: Add virtual GICv3 support
Date: Mon, 28 Jul 2014 17:30:43 +0100
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To: Ian Campbell <Ian.Campbell@citrix.com>
Cc: Vijay Kilari <vijay.kilari@gmail.com>, Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Prasun Kapoor <Prasun.Kapoor@caviumnetworks.com>, Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>, Tim Deegan <tim@xen.org>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>, Stefano Stabellini <stefano.stabellini@citrix.com>, Jan Beulich <jbeulich@suse.com>, manish.jaggi@caviumnetworks.com
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On 07/28/2014 05:25 PM, Ian Campbell wrote:
> On Mon, 2014-07-28 at 17:11 +0100, Julien Grall wrote:
> 
>> It might be worse to add a check in Xen that ICC_SRE_EL3 as the SRE bit
>> enabled.
> 
> I don't think it is readable from EL2.

Oh yes.

FWIW, the Linux documentation say:

"For systems with a GICv3 interrupt controller:
  - If EL3 is present:
    ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
    ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
  - If the kernel is entered at EL1:
    ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
    ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
"

I guess if the firmware doesn't set up correctly those values, then it's
the problem of the firmware developper.

Regards,

-- 
Julien Grall