From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Chen, Tiejun" Subject: Re: [RFC][PATCH 4/5] tools:firmware:hvmloader: reserve RMRR mappings in e820 Date: Tue, 12 Aug 2014 15:59:34 +0800 Message-ID: <53E9C966.9000400@intel.com> References: <1407409371-31728-1-git-send-email-tiejun.chen@intel.com> <1407409371-31728-5-git-send-email-tiejun.chen@intel.com> <53E50EAC020000780002AB89@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <53E50EAC020000780002AB89@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: kevin.tian@intel.com, ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com, ian.jackson@eu.citrix.com, xen-devel@lists.xen.org, yang.z.zhang@intel.com List-Id: xen-devel@lists.xenproject.org On 2014/8/8 23:53, Jan Beulich wrote: >>>> On 07.08.14 at 13:02, wrote: >> We need to reserve all RMRR mappings in e820 to avoid any >> potential guest memory conflict. >> >> Signed-off-by: Tiejun Chen >> --- >> tools/firmware/hvmloader/e820.c | 14 ++++++++++++++ >> tools/firmware/hvmloader/e820.h | 6 ++++++ >> tools/firmware/hvmloader/util.c | 13 +++++++++++++ >> tools/firmware/hvmloader/util.h | 1 + >> 4 files changed, 34 insertions(+) > >> @@ -124,6 +126,18 @@ int build_e820_table(struct e820entry *e820, >> e820[nr].type = E820_RAM; >> nr++; >> >> + /* We'd better reserve RMRR mapping for each VM to avoid potential >> + * memory conflict. >> + */ >> + e820_rmrr_map = get_rmrr_map_info(); >> + for ( i = 0; i <= e820_rmrr_map->nr_map; i++ ) >> + { >> + e820[nr].addr = e820_rmrr_map->map[i].addr; >> + e820[nr].size = e820_rmrr_map->map[i].size + 1; >> + e820[nr].type = E820_RESERVED; >> + nr++; >> + } > > You can't just put this in an arbitrary place, without caring for overlaps > (and ordering perhaps - I don't recall offhand whether E820 is > required to be sorted, or whether that's just common practice). In fact > I'm not certain the code block following your insertion (interestingly > another Intel special) doesn't violate this too. I will add some codes to sort nice in next revision. Thanks Tiejun > > Jan > >