From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH v2 8/9] xen: arm: support for up to 48-bit
 physical addressing on arm64
Date: Mon, 08 Sep 2014 16:28:18 -0700
Message-ID: <540E3B92.8050800@linaro.org>
References: <4427aba8dad3155fca151a0b63bfdf78e3a91033.1409847257.git.ian.campbell@citrix.com>
	<54fd061a6a8fd684f24402d1c431090b292b5126.1409847257.git.ian.campbell@citrix.com>
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To: Ian Campbell <ian.campbell@citrix.com>, xen-devel@lists.xen.org
Cc: tim@xen.org, vijay.kilari@gmail.com, stefano.stabellini@eu.citrix.com
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Hi Ian,

On 04/09/14 09:14, Ian Campbell wrote:
> This only affects Xen's own stage one paging.
>
> - Use symbolic names for TCR bits for clarity.
> - Update PADDR_BITS
> - Base field of LPAE PT structs is now 36 bits (and therefore
>    unsigned long long for arm32 compatibility)
> - TCR_EL2.PS is set from ID_AA64MMFR0_EL1.PASize.
> - Provide decode of ID_AA64MMFR0_EL1 in CPU info
>
> Parts of this are derived from "xen/arm: Add 4-level page table for
> stage 2 translation" by Vijaya Kumar K.
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Reviewed-by: Julien Grall <julien.grall@linaro.org>

Regards,

-- 
Julien Grall