From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH RFC 2/2] xen: arm: Enable physical address space compression (PDX) on arm64 Date: Mon, 08 Sep 2014 17:32:05 -0700 Message-ID: <540E4A85.3030404@linaro.org> References: <53da2211.8511ec0a.4375.46ddSMTPIN_ADDED_MISSING@mx.google.com> <53E3A341.2000502@linaro.org> <1409848806.10156.44.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1409848806.10156.44.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org, Roy Franz , Jan Beulich , Fu Wei List-Id: xen-devel@lists.xenproject.org On 04/09/14 09:40, Ian Campbell wrote: >> I don't really understand what the function is achieving. Could you >> explain a bit more? > > This is largely derived from an x86 equivalent (see srat_parse_regions, > they are different because one walks the device tree RAM and the other > the SRAT), so I hope Jan will correct me if I'm wrong about the > following: > > What it is doing is calculating a mask which corresponds to to the bits > that are active address bits across the valid memory addresses, i.e. a > bit which is necessary to unambiguously represent some valid address is > 1 and a bit which is the same for all addresses is 0. > > Using that mask we then find a large run of zeroes from he middle of the > mask which by construction do not actually get used for addressing. By > omitting those bits from the PFN we obtain a PDX which is the > (losslessly) compressed form. Many thank for the explanation! -- Julien Grall