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From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: tim@xen.org, kevin.tian@intel.com, keir@xen.org,
	suravee.suthikulpanit@amd.com, andrew.cooper3@citrix.com,
	eddie.dong@intel.com, xen-devel@lists.xen.org,
	Aravind.Gopalakrishnan@amd.com, jun.nakajima@intel.com
Subject: Re: [PATCH v10 09/20] x86/VPMU: Add public xenpmu.h
Date: Thu, 11 Sep 2014 12:51:39 -0400	[thread overview]
Message-ID: <5411D31B.90403@oracle.com> (raw)
In-Reply-To: <5411E2F502000078000340BA@mail.emea.novell.com>

On 09/11/2014 11:59 AM, Jan Beulich wrote:
>>>> On 11.09.14 at 17:26, <boris.ostrovsky@oracle.com> wrote:
>> On 09/11/2014 10:55 AM, Jan Beulich wrote:
>>>>>> On 11.09.14 at 15:54, <boris.ostrovsky@oracle.com> wrote:
>>>> On 09/11/2014 02:39 AM, Jan Beulich wrote:
>>>>>>>> On 10.09.14 at 19:23, <boris.ostrovsky@oracle.com> wrote:
>>>>>> On 09/10/2014 10:45 AM, Jan Beulich wrote:
>>>>>>>>>> On 04.09.14 at 05:41, <boris.ostrovsky@oracle.com> wrote:
>>>>>>>> +struct xen_pmu_arch {
>>>>>>>> +    union {
>>>>>>>> +        struct cpu_user_regs regs;
>>>>>>>> +        uint8_t pad[256];
>>>>>>>> +    } r;
>>>>>>> Can you remind me again what you need the union and padding for
>>>>>>> here?
>>>>>> This structure is laid out in a shared page with a (possibly 32-bit)
>>>>>> guest who need to access fields that follow this union.
>>>>> Hmm, okay. But how would such a guest make reasonable use of
>>>>> the regs field then?
>>>> When hypervisor is preparing this data for 32-bit consumer in
>>>> vpmu_do_interrupts() it translates registers to 32-bit version:
>>>>
>>>>            struct compat_cpu_user_regs *cmp;
>>>>            gregs = guest_cpu_user_regs();
>>>>            cmp = (void *)&vpmu->xenpmu_data->pmu.r.regs;
>>>>            XLAT_cpu_user_regs(cmp, gregs);
>>>>
>>>> I remember struggling trying to figure a better way of presenting this
>>>> but ended up with the (void *) cast. IIRC I tried putting
>>>> compat_cpu_user_regs into the union but something didn't quite work
>>>> (with compilation).
>>> Of course that can't work - the compat structure simply doesn't
>>> exist for public headers.
>>>
>>>>> And then - why 256 and not 200? struct
>>>>> cpu_user_regs can't change size anyway. Plus, finally, why do
>>>>> you expose the GPRs but not any of the other register state?
>>>> I wanted to leave some padding in case we decide to add non-GPR
>>>> registers and keep major version of the interface unchanged (only minor
>>>> version will bumped). TBH though, I can't think of any non-GPR registers
>>>> to be ever useful.
>>> Then what do you need the GPRs for here? I don't think they're
>>> any better or worse than, say, XMM ones. I could see you needing/
>>> wanting some basic stuff like CS:RIP and SS:RSP and maybe EFLAGS,
>>> but that's about it.
>> I believe some perf sub-tools (tracing-related if I am not mistaken)
>> want to have access to traced function's arguments.
> And function arguments on x86-64 can very well live in XMM
> registers... Hence no, I still don't see why the registers get
> exposed here in an incomplete/inconsistent fashion.

Linux perf handler takes struct pt_regs as the its sole argument. If we 
pass only few selected registers from hypervisor to the guest then I 
will be passing garbage (partly) to perf.

(I actually do pass that garbage now in my Linux patch but I will be 
fixing this in that series).


-boris

  reply	other threads:[~2014-09-11 16:51 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-04  3:41 [PATCH v10 00/20] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 01/20] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 02/20] x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force() Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 03/20] x86/VPMU: Set MSR bitmaps only for HVM/PVH guests Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 04/20] x86/VPMU: Make vpmu macros a bit more efficient Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 05/20] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 06/20] vmx: Merge MSR management routines Boris Ostrovsky
2014-09-08 16:07   ` Jan Beulich
2014-09-08 17:28     ` Boris Ostrovsky
2014-09-09  9:11       ` Jan Beulich
2014-09-04  3:41 ` [PATCH v10 07/20] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 08/20] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 09/20] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2014-09-10 14:45   ` Jan Beulich
2014-09-10 17:23     ` Boris Ostrovsky
2014-09-11  6:39       ` Jan Beulich
2014-09-11 13:54         ` Boris Ostrovsky
2014-09-11 14:55           ` Jan Beulich
2014-09-11 15:26             ` Boris Ostrovsky
2014-09-11 15:59               ` Jan Beulich
2014-09-11 16:51                 ` Boris Ostrovsky [this message]
2014-09-12  6:50                   ` Jan Beulich
2014-09-12 14:21                     ` Boris Ostrovsky
2014-09-12 14:38                       ` Jan Beulich
2014-09-12 15:18                         ` Boris Ostrovsky
2014-09-15 11:56                           ` Konrad Rzeszutek Wilk
2014-09-15 13:06                             ` Jan Beulich
2014-09-16  1:00                               ` Boris Ostrovsky
2014-09-16  0:49                             ` Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 10/20] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 11/20] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2014-09-10 15:05   ` Jan Beulich
2014-09-10 17:37     ` Boris Ostrovsky
2014-09-11  6:44       ` Jan Beulich
2014-09-11 14:12         ` Boris Ostrovsky
2014-09-11 14:59           ` Jan Beulich
2014-09-11 16:10             ` Boris Ostrovsky
2014-09-12  6:49               ` Jan Beulich
2014-09-12 14:12                 ` Boris Ostrovsky
2014-09-12 14:39                   ` Jan Beulich
2014-09-12 15:03                     ` Boris Ostrovsky
2014-09-12 15:30                       ` Jan Beulich
2014-09-12 15:54                         ` Boris Ostrovsky
2014-09-12 16:05                           ` Jan Beulich
2014-09-12 11:41   ` Dietmar Hahn
2014-09-12 14:25     ` Boris Ostrovsky
2014-09-15 13:35       ` Dietmar Hahn
2014-09-18  4:11   ` Tian, Kevin
2014-09-18 21:50     ` Boris Ostrovsky
2014-09-19  6:51       ` Jan Beulich
2014-09-19 12:42         ` Boris Ostrovsky
2014-09-19 13:28           ` Jan Beulich
2014-09-22 22:29             ` Tian, Kevin
2014-09-22 22:32       ` Tian, Kevin
2014-09-22 22:48         ` Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 12/20] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 13/20] x86/VPMU: When handling MSR accesses, leave fault injection to callers Boris Ostrovsky
2014-09-18  5:01   ` Tian, Kevin
2014-09-04  3:41 ` [PATCH v10 14/20] x86/VPMU: Add support for PMU register handling on PV guests Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 15/20] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
2014-09-10 15:30   ` Jan Beulich
2014-09-04  3:41 ` [PATCH v10 16/20] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr Boris Ostrovsky
2014-09-10 15:33   ` Jan Beulich
2014-09-18  4:16   ` Tian, Kevin
2014-09-04  3:41 ` [PATCH v10 17/20] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2014-09-10 15:39   ` Jan Beulich
2014-09-04  3:41 ` [PATCH v10 18/20] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2014-09-10 15:44   ` Jan Beulich
2014-09-04  3:41 ` [PATCH v10 19/20] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
2014-09-04  3:41 ` [PATCH v10 20/20] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
2014-09-10 15:48   ` Jan Beulich
2014-09-10 15:54 ` [PATCH v10 00/20] x86/PMU: Xen PMU PV(H) support Jan Beulich

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