From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH] x86/vlapic: don't silently accept bad vectors Date: Mon, 15 Sep 2014 15:40:46 +0100 Message-ID: <5416FA6E.9000505@citrix.com> References: <5416EF510200007800034F54@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============6682696934432369177==" Return-path: Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XTXU9-0005L0-FC for xen-devel@lists.xenproject.org; Mon, 15 Sep 2014 14:42:33 +0000 In-Reply-To: <5416EF510200007800034F54@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich , xen-devel Cc: Keir Fraser List-Id: xen-devel@lists.xenproject.org This is a multi-part message in MIME format. --===============6682696934432369177== Content-Type: multipart/alternative; boundary="------------080607070201060303010801" This is a multi-part message in MIME format. --------------080607070201060303010801 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On 15/09/2014 12:53, Jan Beulich wrote: > Vectors 0-15 are reserved, and a physical LAPIC - upon sending or > receiving one - would generate an APIC error instead of doing the > requested action. Make our emulation behave similarly. > > Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper > --- > This only applies cleanly on top of the two earlier series > http://lists.xenproject.org/archives/html/xen-devel/2014-09/msg01751.html > http://lists.xenproject.org/archives/html/xen-devel/2014-09/msg02101.html > > --- a/xen/arch/x86/hvm/vlapic.c > +++ b/xen/arch/x86/hvm/vlapic.c > @@ -123,10 +123,34 @@ static int vlapic_find_highest_irr(struc > return vlapic_find_highest_vector(&vlapic->regs->data[APIC_IRR]); > } > > +static void vlapic_error(struct vlapic *vlapic, unsigned int errmask) > +{ > + unsigned long flags; > + uint32_t esr; > + > + spin_lock_irqsave(&vlapic->esr_lock, flags); > + esr = vlapic_get_reg(vlapic, APIC_ESR); > + if ( (esr & errmask) != errmask ) > + { > + uint32_t lvterr = vlapic_get_reg(vlapic, APIC_LVTERR); > + > + vlapic_set_reg(vlapic, APIC_ESR, esr | errmask); > + if ( !(lvterr & APIC_LVT_MASKED) ) > + vlapic_set_irq(vlapic, lvterr & APIC_VECTOR_MASK, 0); > + } > + spin_unlock_irqrestore(&vlapic->esr_lock, flags); > +} > + > void vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig) > { > struct vcpu *target = vlapic_vcpu(vlapic); > > + if ( unlikely(vec < 16) ) > + { > + vlapic_error(vlapic, APIC_ESR_RECVILL); > + return; > + } > + > if ( trig ) > vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]); > > @@ -459,7 +483,12 @@ void vlapic_ipi( > struct vlapic *target = vlapic_lowest_prio( > vlapic_domain(vlapic), vlapic, short_hand, dest, dest_mode); > if ( target != NULL ) > - vlapic_accept_irq(vlapic_vcpu(target), icr_low); > + { > + if ( likely((icr_low & APIC_VECTOR_MASK) >= 16) ) > + vlapic_accept_irq(vlapic_vcpu(target), icr_low); > + else > + vlapic_error(vlapic, APIC_ESR_SENDILL); > + } > break; > } > > @@ -467,6 +496,11 @@ void vlapic_ipi( > struct vcpu *v; > bool_t batch = is_multicast_dest(vlapic, short_hand, dest, dest_mode); > > + if ( unlikely((icr_low & APIC_VECTOR_MASK) < 16) ) > + { > + vlapic_error(vlapic, APIC_ESR_SENDILL); > + break; > + } > if ( batch ) > cpu_raise_softirq_batch_begin(); > for_each_vcpu ( vlapic_domain(vlapic), v ) > @@ -1349,6 +1383,8 @@ int vlapic_init(struct vcpu *v) > if ( v->vcpu_id == 0 ) > vlapic->hw.apic_base_msr |= MSR_IA32_APICBASE_BSP; > > + spin_lock_init(&vlapic->esr_lock); > + > tasklet_init(&vlapic->init_sipi.tasklet, > vlapic_init_sipi_action, > (unsigned long)v); > --- a/xen/include/asm-x86/hvm/vlapic.h > +++ b/xen/include/asm-x86/hvm/vlapic.h > @@ -73,6 +73,7 @@ > struct vlapic { > struct hvm_hw_lapic hw; > struct hvm_hw_lapic_regs *regs; > + spinlock_t esr_lock; > bool_t loaded; > struct periodic_time pt; > s_time_t timer_last_update; > > > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel --------------080607070201060303010801 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit
On 15/09/2014 12:53, Jan Beulich wrote:
Vectors 0-15 are reserved, and a physical LAPIC - upon sending or
receiving one - would generate an APIC error instead of doing the
requested action. Make our emulation behave similarly.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

---
This only applies cleanly on top of the two earlier series
http://lists.xenproject.org/archives/html/xen-devel/2014-09/msg01751.html 
http://lists.xenproject.org/archives/html/xen-devel/2014-09/msg02101.html 

--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -123,10 +123,34 @@ static int vlapic_find_highest_irr(struc
     return vlapic_find_highest_vector(&vlapic->regs->data[APIC_IRR]);
 }
 
+static void vlapic_error(struct vlapic *vlapic, unsigned int errmask)
+{
+    unsigned long flags;
+    uint32_t esr;
+
+    spin_lock_irqsave(&vlapic->esr_lock, flags);
+    esr = vlapic_get_reg(vlapic, APIC_ESR);
+    if ( (esr & errmask) != errmask )
+    {
+        uint32_t lvterr = vlapic_get_reg(vlapic, APIC_LVTERR);
+
+        vlapic_set_reg(vlapic, APIC_ESR, esr | errmask);
+        if ( !(lvterr & APIC_LVT_MASKED) )
+            vlapic_set_irq(vlapic, lvterr & APIC_VECTOR_MASK, 0);
+    }
+    spin_unlock_irqrestore(&vlapic->esr_lock, flags);
+}
+
 void vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig)
 {
     struct vcpu *target = vlapic_vcpu(vlapic);
 
+    if ( unlikely(vec < 16) )
+    {
+        vlapic_error(vlapic, APIC_ESR_RECVILL);
+        return;
+    }
+
     if ( trig )
         vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]);
 
@@ -459,7 +483,12 @@ void vlapic_ipi(
         struct vlapic *target = vlapic_lowest_prio(
             vlapic_domain(vlapic), vlapic, short_hand, dest, dest_mode);
         if ( target != NULL )
-            vlapic_accept_irq(vlapic_vcpu(target), icr_low);
+        {
+            if ( likely((icr_low & APIC_VECTOR_MASK) >= 16) )
+                vlapic_accept_irq(vlapic_vcpu(target), icr_low);
+            else
+                vlapic_error(vlapic, APIC_ESR_SENDILL);
+        }
         break;
     }
 
@@ -467,6 +496,11 @@ void vlapic_ipi(
         struct vcpu *v;
         bool_t batch = is_multicast_dest(vlapic, short_hand, dest, dest_mode);
 
+        if ( unlikely((icr_low & APIC_VECTOR_MASK) < 16) )
+        {
+            vlapic_error(vlapic, APIC_ESR_SENDILL);
+            break;
+        }
         if ( batch )
             cpu_raise_softirq_batch_begin();
         for_each_vcpu ( vlapic_domain(vlapic), v )
@@ -1349,6 +1383,8 @@ int vlapic_init(struct vcpu *v)
     if ( v->vcpu_id == 0 )
         vlapic->hw.apic_base_msr |= MSR_IA32_APICBASE_BSP;
 
+    spin_lock_init(&vlapic->esr_lock);
+
     tasklet_init(&vlapic->init_sipi.tasklet,
                  vlapic_init_sipi_action,
                  (unsigned long)v);
--- a/xen/include/asm-x86/hvm/vlapic.h
+++ b/xen/include/asm-x86/hvm/vlapic.h
@@ -73,6 +73,7 @@
 struct vlapic {
     struct hvm_hw_lapic      hw;
     struct hvm_hw_lapic_regs *regs;
+    spinlock_t               esr_lock;
     bool_t                   loaded;
     struct periodic_time     pt;
     s_time_t                 timer_last_update;






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