From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: kevin.tian@intel.com, keir@xen.org,
Jan Beulich <JBeulich@suse.com>,
jun.nakajima@intel.com, andrew.cooper3@citrix.com, tim@xen.org,
xen-devel@lists.xen.org, eddie.dong@intel.com,
Aravind.Gopalakrishnan@amd.com, suravee.suthikulpanit@amd.com
Subject: Re: [PATCH v10 09/20] x86/VPMU: Add public xenpmu.h
Date: Mon, 15 Sep 2014 20:49:15 -0400 [thread overview]
Message-ID: <5417890B.7070101@oracle.com> (raw)
In-Reply-To: <20140915115635.GA4831@laptop.dumpdata.com>
On 09/15/2014 07:56 AM, Konrad Rzeszutek Wilk wrote:
> On Fri, Sep 12, 2014 at 11:18:48AM -0400, Boris Ostrovsky wrote:
>> On 09/12/2014 10:38 AM, Jan Beulich wrote:
>>>>>> On 12.09.14 at 16:21, <boris.ostrovsky@oracle.com> wrote:
>>>> On 09/12/2014 02:50 AM, Jan Beulich wrote:
>>>>> Okay, so you're tailoring the hypervisor interface to Linux. That's
>>>>> not what we generally aim for, and hence I continue to think this
>>>>> isn't the right approach.
>>>> But we know that at least one consumer of this interface (Linux/perf)
>>>> does want to have full GPR set.
>>> You said they use a struct pt_regs somewhere - that's not the same
>>> as struct cpu_user_regs (and the overlap of registers being in both
>>> is not much more than a coincidence), and you didn't clarify yet how
>>> much of this information is _actually_ getting consumed (i.e. this may
>>> well just happen to be a suitable container for conveying a smaller
>>> set).
>> I don't know how all registers are consumed in Linux code (except for RIP
>> and CS) and I am not sure it's all that important: we know that we need to
>> pass GPRs to perf infrastructure which, for the most part, is a black box
>> (especially given the insane amount of code churn that happens in perf).
>>
>> If and when we find out that something that perf wants is not provided in
>> pt_regs (converted from cpu_user_regs) then we will have to deal with it.
>> But it's not much different from what would happen if we use specific
>> registers in the shared structure.
>>
>>>> So why not provide it? Especially since
>>>> (I suspect that) doing memcpy may be faster than copying only selected
>>>> fields.
>>>>
>>>> If you are categorically against this I can certainly rework this and
>>>> pass RIP, RSP, CS and EFLAGS only.
>>> My problem with this is that (a) it exposes an arbitrary subset of
>>> registers and (b) in an incompatible way (a 32-bit profiling domain
>>> should very well be told all 64-bit registers of a 64-bit guest it
>>> profiles). Since b would need addressing by a custom structure
>>> anyway, dealing with a at the same time seems reasonable to me.
>> Note that (b) is not supported --- 32-bit domains can only profile
>> themselves and not the hypervisor (or other domains).
> And that is due to the tools limitation of not being able to understand
> 64-bit values right?.
Right. Specifically, in perf case it will be very surprised to see
64-bit samples (in fact, it won't see them as 64-bit since registers
that it sees are 32-bit).
>
>>> But of course it would help if other interested parties would voice
>>> their view of this...
> My thinking (with the release manager hat) is thishat:
>
> 1). Adding in the support for 32-bit consumer is nice but won't be
> used that often (64-bit consumer with 32-bit 'producer' - as in
> 32-bit guests - will surely be present).
Profiling hypervisor from 32-bit dom0 is not planned at all. This will
require new toolset.
>
> 2). Having the right ABI for these perf counters is hard across
> two set of vendors (and what if we want to expand this for ARM?).
Intel/AMD, I think/hope, is taken care of.
ARM is now stubbed out, most of the code is in x86-specific directory.
-boris
>
> 3). The one 'generic' profiling tool that worked across all OSes
> was 'oprofile' which has hit the dustpan. We still support
> it with the oprofile hypercalls. Doing something generic
> might not be the best way going forward.
>
> 4). The ABI should have means to look in the future in case things
> change (and then there is a method to provide the version information
> in case the ABI alters). Future version of the Intel
> or AMD performance counters architecture might expand the
> amount of registers they expose. Or they might not.
> Either way, a new minor rev would have to be increased to
> benefit from this.
>
> 5). Exposing only CS, RIP, and EFLAGS seems to be tailoring the
> interface for Linux perf use case.
>
> 6). Exposing all of the GPRs, while not needed for the current
> set of Linux patches, could allow other tools to use this
> (Intel's tracing tool for example - which uses the perf
> ABI). But surely there are tools on FreeBSD, NetBSD that
> do profiling.
>
>
> If I understand Jan's concerns correctly, the question is -
> if we are not using all of the GPRs right now in the tools
> why even bother expanding it? And if the new version of
> the architecture does expose it - and we have the support
> - then we can expand the page structure? (and of course
> rev the major).
>
> While Boris's view is that the condition above will happen -
> we will expand the registers/use case - so why do the
> intermediate step of expanding the page structure - when we can
> make the structure bigger now (and rev the minor).
>
> Is that about right?
next prev parent reply other threads:[~2014-09-16 0:49 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-04 3:41 [PATCH v10 00/20] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 01/20] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 02/20] x86/VPMU: Manage VPMU_CONTEXT_SAVE flag in vpmu_save_force() Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 03/20] x86/VPMU: Set MSR bitmaps only for HVM/PVH guests Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 04/20] x86/VPMU: Make vpmu macros a bit more efficient Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 05/20] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 06/20] vmx: Merge MSR management routines Boris Ostrovsky
2014-09-08 16:07 ` Jan Beulich
2014-09-08 17:28 ` Boris Ostrovsky
2014-09-09 9:11 ` Jan Beulich
2014-09-04 3:41 ` [PATCH v10 07/20] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 08/20] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 09/20] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2014-09-10 14:45 ` Jan Beulich
2014-09-10 17:23 ` Boris Ostrovsky
2014-09-11 6:39 ` Jan Beulich
2014-09-11 13:54 ` Boris Ostrovsky
2014-09-11 14:55 ` Jan Beulich
2014-09-11 15:26 ` Boris Ostrovsky
2014-09-11 15:59 ` Jan Beulich
2014-09-11 16:51 ` Boris Ostrovsky
2014-09-12 6:50 ` Jan Beulich
2014-09-12 14:21 ` Boris Ostrovsky
2014-09-12 14:38 ` Jan Beulich
2014-09-12 15:18 ` Boris Ostrovsky
2014-09-15 11:56 ` Konrad Rzeszutek Wilk
2014-09-15 13:06 ` Jan Beulich
2014-09-16 1:00 ` Boris Ostrovsky
2014-09-16 0:49 ` Boris Ostrovsky [this message]
2014-09-04 3:41 ` [PATCH v10 10/20] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 11/20] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2014-09-10 15:05 ` Jan Beulich
2014-09-10 17:37 ` Boris Ostrovsky
2014-09-11 6:44 ` Jan Beulich
2014-09-11 14:12 ` Boris Ostrovsky
2014-09-11 14:59 ` Jan Beulich
2014-09-11 16:10 ` Boris Ostrovsky
2014-09-12 6:49 ` Jan Beulich
2014-09-12 14:12 ` Boris Ostrovsky
2014-09-12 14:39 ` Jan Beulich
2014-09-12 15:03 ` Boris Ostrovsky
2014-09-12 15:30 ` Jan Beulich
2014-09-12 15:54 ` Boris Ostrovsky
2014-09-12 16:05 ` Jan Beulich
2014-09-12 11:41 ` Dietmar Hahn
2014-09-12 14:25 ` Boris Ostrovsky
2014-09-15 13:35 ` Dietmar Hahn
2014-09-18 4:11 ` Tian, Kevin
2014-09-18 21:50 ` Boris Ostrovsky
2014-09-19 6:51 ` Jan Beulich
2014-09-19 12:42 ` Boris Ostrovsky
2014-09-19 13:28 ` Jan Beulich
2014-09-22 22:29 ` Tian, Kevin
2014-09-22 22:32 ` Tian, Kevin
2014-09-22 22:48 ` Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 12/20] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 13/20] x86/VPMU: When handling MSR accesses, leave fault injection to callers Boris Ostrovsky
2014-09-18 5:01 ` Tian, Kevin
2014-09-04 3:41 ` [PATCH v10 14/20] x86/VPMU: Add support for PMU register handling on PV guests Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 15/20] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
2014-09-10 15:30 ` Jan Beulich
2014-09-04 3:41 ` [PATCH v10 16/20] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr Boris Ostrovsky
2014-09-10 15:33 ` Jan Beulich
2014-09-18 4:16 ` Tian, Kevin
2014-09-04 3:41 ` [PATCH v10 17/20] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2014-09-10 15:39 ` Jan Beulich
2014-09-04 3:41 ` [PATCH v10 18/20] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2014-09-10 15:44 ` Jan Beulich
2014-09-04 3:41 ` [PATCH v10 19/20] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
2014-09-04 3:41 ` [PATCH v10 20/20] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
2014-09-10 15:48 ` Jan Beulich
2014-09-10 15:54 ` [PATCH v10 00/20] x86/PMU: Xen PMU PV(H) support Jan Beulich
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