From: David Vrabel <david.vrabel@citrix.com>
To: Jan Beulich <JBeulich@suse.com>, Roger Pau Monne <roger.pau@citrix.com>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH v2] docs: add PVH specification
Date: Thu, 18 Sep 2014 17:03:45 +0100 [thread overview]
Message-ID: <541B0261.5080904@citrix.com> (raw)
In-Reply-To: <541B1CFD020000780003643F@mail.emea.novell.com>
On 18/09/14 16:57, Jan Beulich wrote:
>>>> On 18.09.14 at 17:27, <roger.pau@citrix.com> wrote:
>> +All the segments selectors are set with a flat base at zero.
>> +
>> +The `cs` segment selector attributes are set to 0x0a09b, which describes an
>> +executable and readable code segment only accessible by the most privileged
>> +level. The segment is also set as a 64-bit code segment (`L` flag set) with a
>> +default operation size of 16bits (`D` flag unset).
>
> There's no such thing - the L bit set requires the D bit to be clear
> _without_ this meaning a default operation size of 16 bits.
>
>> +The remaining segment selectors (`ds`, `ss`, `es`, `fs` and `gs`) are all set
>> +to the same values. The attributes are set to 0x0c093, which implies a read and
>> +write data segment only accessible by the most privileged level. It is important
>> +to notice that for the `ss` selector the stack is set to use a 32bit pointer
>> +(`B` flag set).
>
> The B bit really has no meaning in 64-bit mode, and the stack pointer
> will always be a 64-bit one.
Perhaps this doc should avoid explaining what the bits mean? The Intel
or AMD reference manuals can be used for this.
David
next prev parent reply other threads:[~2014-09-18 16:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-18 15:27 [PATCH v2] docs: add PVH specification Roger Pau Monne
2014-09-18 15:46 ` David Vrabel
2014-09-18 15:57 ` Jan Beulich
2014-09-18 16:03 ` David Vrabel [this message]
2014-09-19 6:21 ` Jan Beulich
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