From: Andre Przywara <andre.przywara@linaro.org>
To: Julien Grall <julien.grall@linaro.org>,
Stefano Stabellini <sstabellini@kernel.org>,
Manish Jaggi <manish.jaggi@linaro.org>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH] arm64: ITS: fix cacheability adjustment
Date: Tue, 28 Nov 2017 14:05:58 +0000 [thread overview]
Message-ID: <541ca3dc-1cb6-f1e4-6355-3e2a59812604@linaro.org> (raw)
In-Reply-To: <20171116120235.10041-1-andre.przywara@linaro.org>
Hi,
On 16/11/17 12:02, Andre Przywara wrote:
> If the host GICv3 redistributor reports that the pending table cannot
> use shareable memory, we try to drop the cacheability attributes as
> well. However we fail horribly in doing computer science 101 bit
> masking, effectively clearing the whole register instead of just a few
> bits.
> Fix this by removing the one redundant masking operation and adding the
> magic negation for the actually needed other operation.
>
> Reported-by: Manish Jaggi <manish.jaggi@linaro.org>
Manish, can you please test this patch and confirm that it works?
Also how does the bug manifest for you?
Julien, Stefano: Are there any objections against taking this patch for
4.10? This was introduced with the ITS emulation.
Cheers,
Andre.
> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
> ---
> Julien,
>
> can we have this still for 4.10, please? Seems like an obvious bug to me.
>
> Cheers,
> Andre
>
> xen/arch/arm/gic-v3-lpi.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
> index c3474f5434..84582157b8 100644
> --- a/xen/arch/arm/gic-v3-lpi.c
> +++ b/xen/arch/arm/gic-v3-lpi.c
> @@ -359,8 +359,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base)
> /* If the hardware reports non-shareable, drop cacheability as well. */
> if ( !(table_reg & GICR_PENDBASER_SHAREABILITY_MASK) )
> {
> - table_reg &= GICR_PENDBASER_SHAREABILITY_MASK;
> - table_reg &= GICR_PENDBASER_INNER_CACHEABILITY_MASK;
> + table_reg &= ~GICR_PENDBASER_INNER_CACHEABILITY_MASK;
> table_reg |= GIC_BASER_CACHE_nC << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT;
>
> writeq_relaxed(table_reg, rdist_base + GICR_PENDBASER);
>
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next prev parent reply other threads:[~2017-11-28 14:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-16 12:02 [PATCH] arm64: ITS: fix cacheability adjustment Andre Przywara
2017-11-28 14:05 ` Andre Przywara [this message]
2017-11-28 19:01 ` Julien Grall
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