From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: xen:arm boot failures after commit 1c92a2aa* Date: Wed, 24 Sep 2014 16:58:29 +0100 Message-ID: <5422EA25.9080705@linaro.org> References: <1411561579.28127.26.camel@kazak.uk.xensource.com> <1411568192.28127.40.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1411568192.28127.40.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , Suriyan Ramasami Cc: "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org Hi Ian, On 09/24/2014 03:16 PM, Ian Campbell wrote: > On Wed, 2014-09-24 at 05:36 -0700, Suriyan Ramasami wrote: > Thanks, > >> (XEN) VTCR_EL2: 80003518 > > THis has changed from 0x80003558 before this change (sorry, this was in > your original report too and I failed to spot it). > > The missing bit changes the starting level of the PT from L1 to L2, > which ain't gonna work very well ;-). > > I can't for the life of me figure out how/why this works on arndale, but > it does... It also works on Midway (without the patch below). I guess it depends on the position of the RAM in the p2m. > Anyway, does this fix it for you? > > 8<------------------ > > From ada27d3a56ba89513721e24abe4a4bebee2ab9cf Mon Sep 17 00:00:00 2001 > From: Ian Campbell > Date: Wed, 24 Sep 2014 15:13:28 +0100 > Subject: [PATCH] xen: arm: correct VTCR setting on arm32. > > 1c92a2aaf8c6 "xen: arm: support for up to 48-bit IPA addressing on > arm64" inadvertently changes the VTCR setting for 32-bit from > 0x80003558 to 0x80003518, changing the SL0 setting from 0x1 (p2m > starts at L1) to 0x0 (p2m starts at L2). > > For some (inexplicable) reason this doesn't cause any issue on > Arndale but it does on the OdroidXU. > > Reported-by: Suriyan Ramasami > Signed-off-by: Ian Campbell Reviewed-by: Julien Grall Regards, -- Julien Grall