From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH v17 08/10] x86: add CMT related MSRs in allowed list Date: Mon, 29 Sep 2014 15:09:09 +0100 Message-ID: <54296805.7050901@citrix.com> References: <1411987239-3509-1-git-send-email-chao.p.peng@linux.intel.com> <1411987239-3509-9-git-send-email-chao.p.peng@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1411987239-3509-9-git-send-email-chao.p.peng@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Chao Peng , xen-devel@lists.xen.org Cc: keir@xen.org, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, George.Dunlap@eu.citrix.com, Ian.Jackson@eu.citrix.com, JBeulich@suse.com, dgdegra@tycho.nsa.gov List-Id: xen-devel@lists.xenproject.org On 29/09/14 11:40, Chao Peng wrote: > Tool stack will try to access the two MSRs to perform CMT > related operations, thus added them in the allowed list. > > Signed-off-by: Dongxiao Xu > Signed-off-by: Chao Peng Reviewed-by: Andrew Cooper > --- > xen/arch/x86/platform_hypercall.c | 8 ++++++++ > xen/include/asm-x86/msr-index.h | 2 ++ > 2 files changed, 10 insertions(+) > > diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c > index 4b92b56..c049499 100644 > --- a/xen/arch/x86/platform_hypercall.c > +++ b/xen/arch/x86/platform_hypercall.c > @@ -69,6 +69,14 @@ struct xen_resource_access { > > static bool_t allow_access_msr(unsigned int msr) > { > + switch ( msr ) > + { > + /* MSR for CMT, refer to chapter 17.14 of Intel SDM. */ > + case MSR_IA32_QOSEVTSEL: > + case MSR_IA32_QMC: > + return 1; > + } > + > return 0; > } > > diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h > index dcb2b87..ae089fb 100644 > --- a/xen/include/asm-x86/msr-index.h > +++ b/xen/include/asm-x86/msr-index.h > @@ -324,6 +324,8 @@ > #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 > > /* Platform Shared Resource MSRs */ > +#define MSR_IA32_QOSEVTSEL 0x00000c8d > +#define MSR_IA32_QMC 0x00000c8e > #define MSR_IA32_PQR_ASSOC 0x00000c8f > > /* Intel Model 6 */