Re: [PATCH 6/9] xen: arm: Handle CP14 32-bit register accesses from userspace

[Julien Grall <julien.grall@linaro.org>]

On 10/02/2015 11:40, Ian Campbell wrote:
> On Wed, 2014-09-10 at 10:48 +0100, Ian Campbell wrote:
>> On Tue, 2014-09-09 at 16:45 -0700, Julien Grall wrote:
>>> Hi Ian,
>>>
>>> On 09/09/14 09:23, Ian Campbell wrote:
>>>> Accesses to these from 32-bit userspace would cause a hypervisor exception
>>>> (host crash) when running a 64-bit kernel, which is worked around by the fix to
>>>> XSA-102. On 32-bit kernels they would be implemented as RAZ/WI which is
>>>> incorrect but harmless.
>>>>
>>>> Update as follows:
>>>>    - DBGDSCRINT should be R/O.
>>>>    - DBGDSCREXT should be EL1 only.
>>>>    - DBGOSLAR is RO and EL1 only.
>>>>    - DBGVCR, DBGB[VC]R*, DBGW[VC]R*, and DBGOSDLR are EL1 only.
>>>>
>>>> DBGDIDR and DBGDSCRINT are accessible from EL0 if DBGDSCRext.UDCCdis. Since we
>>>> emulate that as RAZ/WI we allow access.
>>>
>>> Shall we just set DBGDSCRext.UDCCdis to avoid taking care of EL0 access?
>>
>> I'd need to lookup what the acceptable reset states for that bit are,
>> but perhaps.
>
> The AArch32 version of this bit resets to 0, so I think the code is OK
> as it is, at least for now.
>
> I'd like to implement proper handling of dbg registers sooner rather
> than later, but I think this series should go in first and the the dbg
> stuff can be built on it later.

I'm fine with that. Let's have a 32-bit userspace support on 64-bit 
kernel before :).

Regards,


-- 
Julien Grall